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PDF HI-8590 Data sheet ( Hoja de datos )
| Número de pieza | HI-8590 | |
| Descripción | ARINC 429 LINE DRIVER AND DUAL RECEIVER | |
| Fabricantes | Holt Integrated Circuits | |
| Logotipo |  |
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January 2001
HI-8590
ARINC 429 LINE DRIVER AND LINE RECEIVER
DESCRIPTION
The HI-8590 is a CMOS integrated circuit with independ-
ent ARINC 429 line driver and line receiver in a single
16 pin package. Both ARINC 429 functions are imple-
mented in analog/digital CMOS.
The line driver function in the HI-8590 connects directly to
the ARINC bus and translates CMOS/TTL input levels to
ARINC 429 specified amplitudes using built-in zeners.
The slope of the differential output signal is controlled by a
single logic input without the use of any external capaci-
tors. A internal 37.5 ohm resistor is provided in series with
each line driver output. The line driver function is the
same as Holt's 8 pin stand-alone HI-8585 line driver.
The line receiver interfaces directly to the ARINC 429 bus
and translates incoming ARINC levels to levels compati-
ble with CMOS logic. Internal comparator levels are set
just below the standard 6.5 volt minimum data threshold
and just above the standard 2.5 volt maximum null thresh-
old
The TESTA and TESTB inputs of the line receiver allow
bypassing the analog input circuitry for testing purposes.
Also, if both test inputs are taken high, the receiver's digital
outputs are tri-stated allowing wire-or possibilities. The
line driver function is the same as Holt's 8 pin stand-alone
HI-8588 line receiver.
FEATURES
! Direct ARINC 429 interface to line driver
and line receiver
! Both functions in a single 16 pin package
! Line Driver
! Internal zener sets output levels
! Digital output slope control
! CMOS/TTL logic pins
! Line Receiver
! Input hystersis at least 2 volts
! Test inputs bypass analog inputs
! Output tri-state mode
! Plastic thermally enhanced surface
mount (ESOIC) package
! Mil-temperature range available
PIN CONFIGURATION
V+ 1
TESTB 2
ROUTB 3
ROUTA 4
TXBOUT 5
TXAOUT 6
N/C 7
V- 8
16 VCC
15 SLP1.5
14 TESTA
13 RINB
12 RINA
11 TX0IN
10 TX1IN
9 GND
SUPPLY VOLTAGES
Vcc = +5V ± 5%
V+ = 12V to 15V
V- = -12V to -15V
PIN DESCRIPTION TABLE
PIN SYMBOL
FUNCTION
DESCRIPTION
1 V+
POWER
+12 TO + 15 VOLTS
2 TESTB
LOGIC INPUT CMOS
3 ROUTB
LOGIC OUTPUT RECEIVER CMOS OUTPUT B
4 ROUTA
LOGIC OUTPUT RECEIVER CMOS OUTPUT A
5 TXBOUT
ARINC OUTPUT LINE DRIVER TERMINAL B
6 TXAOUT
ARINC OUTPUT LINE DRIVER TERMINAL A
7 N/C
NO CONNECT
8 V-
POWER
-12 TO -15 VOLTS
9 GND
POWER
GROUND
10 TX1IN
LOGIC INPUT CMOS OR TTL
11 TX0IN
LOGIC INPUT CMOS OR TTL
12 RINA
ARINC INPUT RECEIVER A INPUT
13 RINB
ARINC INPUT RECEIVER B INPUT
14 TESTA
LOGIC INPUT CMOS
15 SLP1.5
LOGIC INPUT CMOS OR TTL, V+ IS OK
16 VCC
POWER
+5 VOLT SUPPLY
(DS8590 Rev. B)
HOLT INTEGRATED CIRCUITS
1
01/01
1 page  
HI-8590
DC ELECTRICAL CHARACTERISTICS (cont.)
Vcc = 5V ±5%, V+ = 12V to 15V, V- = -12V to -15V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETERS
SYMBOL TEST CONDITIONS
MIN TYP MAX UNITS
Line Receiver
ARINC input voltage (RINA, RINB)
one or zero
null
common mode
VDIN
VNIN
VCOM
differential voltage
""
with respect to GND
6.5 10.0 13.0
- - 2.5
- - 5.0
volts
volts
volts
Logic input voltage (TESTA, TESTB)
high
low
VIH
VIL
3.5 -
- volts
- - 1.5 volts
ARINC input resistance
RINA to RINB
RINA or RINB to GND or VCC
RDIFF
RSUP
supplies floating
""
30 75
19 40
- Kohm
- Kohm
Logic input current (TESTA, TESTB)
source
sink
IIH VIN = 0V
IIL VIN = 5V
- - 0.1 µA
- - 0.1 µA
Logic output current (ROUTA, ROUTB)
one
zero
IOH VOH = 4.6V
IOL VOL = 0.4V
- -1.6 -0.8 mA
3.6 5.6 - mA
Operating Supply Current
VCC - operating (TESTA & TESTB = 0V)
ICC
RINA, RINB open
V+ = +15V
- 5.3 8.5 mA
V+
IDD no load
- 6.0 12.0 mA
SLP1.5 = V+
V-
IEE TX1IN, TX0IN = 0V
-12.0 -6.0 - mA
AC ELECTRICAL CHARACTERISTICS
Vcc = 5V ±5%, V+ = 12V to 15V, V- = -12V to -15V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETERS
SYMBOL TEST CONDITIONS
MIN TYP MAX UNITS
Line Driver
Propagation delay
Output high to low
Output low to high
defined in Figure 4, no load
t phlx
t plhx
- 500 -
- 500 -
ns
ns
Transition times
Output high to low & low to high
Output high to low & low to high
t fx & t rx
t fx & t rx
SLP1.5 = logic 1
SLP1.5 = logic 0
1.0 1.5 2.0
5 10 15
µs
µs
Line driver input capacitance
Logic
CIN Guaranteed but not tested -
- 10 pF
HOLT INTEGRATED CIRCUITS
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet HI-8590.PDF ] | |
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