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PDF HI-8581 Data sheet ( Hoja de datos )
| Número de pieza | HI-8581 | |
| Descripción | ARINC 429 LINE DRIVER AND DUAL RECEIVER | |
| Fabricantes | Holt Integrated Circuits | |
| Logotipo |  |
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HI-8581
June 2001
GENERAL DESCRIPTION
The HI-8581 device from Holt Integrated Circuits is a silicon
gate CMOS device for interfacing a 16-bit parallel data bus
directly to the ARINC 429 serial bus. The device provides
two receivers, an independent transmitter and line driver
capability in a single package. The receiver input circuitry
and logic are designed to meet the ARINC 429
specifications for loading, level detection, timing, and
protocol. The transmitter section provides the ARINC 429
communication protocol and the line driver circuits provide
the ARINC 429 output levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces with
CMOS and TTL.
Timing of all the circuitry begins with the master clock input,
CLK. For ARINC 429 applications, the master clock
frequency is 1 MHz.
Each independent receiver monitors the data stream with a
sampling rate 10 times the data rate. The sampling rate is
software selectable at either 1MHz or 125KHz. The results
of a parity check are available as the 32nd ARINC bit. The
HI-8581 examines the null and data timings and will reject
erroneous patterns. For example, with a 125 KHz clock
selection, the data frequency must be between 10.4 KHz
and 15.6 KHz.
The transmitter has a First In, First Out (FIFO) memory to
store 8 ARINC words for transmission. The data rate of the
transmitter is software selectable by dividing the master
clock, CLK, by either 10 or 80. The master clock is used to
set the timing of the ARINC transmission within the required
resolution.
APPLICATIONS
! Avionics data communication
! Serial to parallel conversion
! Parallel to serial conversion
FEATURES
! ARINC specification 429 compatible
! Direct receiver and transmitter interface to
ARINC bus in a single device.
! 16-Bit parallel data bus.
! Timing control 10 times the data rate
! Selectable data clocks
! Receiver error rejection per ARINC
specification 429
! Automatic transmitter data timing
! Self test mode
! Parity functions
! Low power
! Industrial & full military temperature ranges
PIN CONFIGURATION (Top View)
429DI2(B) - 1
D/R1 - 2
D/R2 - 3
SEL - 4
EN1 - 5
EN2 - 6
BD15 - 7
BD14 - 8
BD13 - 9
BD12 - 10
BD11 - 11
HI-8581PQI
&
HI-8581PQT
33 - ENTX
32 - N/C
31 - V+
30 - TXB(OUT)
29 - TXA(OUT)
28 - V-
27 - GND
26 - TX/R
25 - PL2
24 - PL1
23 - BD00
(See page 13 for additional pin configurations)
(DS8581 Rev. A)
HOLT INTEGRATED CIRCUITS
1
06/01
1 page  
HI-8581
TRANSMITTER
A block diagram of the transmitter section is shown in Figure 3.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either 429DO or 429DO. The 31 bits in the
data transmission shift register are presented sequentially to the
outputs in the ARINC 429 format with the following timing:
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
The word counter detects when all loaded positions are
transmitted and sets the transmitter ready flag, TX/R, high.
TRANSMITTER PARITY
The parity generator counts the ONES in the 31-bit word. If the
BD12 control word bit is set low, the 32nd bit transmitted will
make parity odd. If the control bit is high, the parity is even.
SELF TEST
If the BD05 control word bit is set low, 429DO or 429DO become
inputs to the receiver bypassing the interface circuitry.
SYSTEM OPERATION
The two receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The
only restrictions are:
1. The received data may be overwritten if not retrieved
within one ARINC word cycle.
2. The FIFO can store 8 words maximum and ignores
attempts to load addition data if full.
3. Byte 1 of the transmitter data must be loaded first.
4. Either byte of the received data may be retrieved first.
Both bytes must be retrieved to clear the data ready flag.
5. After ENTX, transmission enable, goes high it cannot go
low until TX/R, transmitter ready flag, goes high. Otherwise,
one ARINC word is lost during transmission.
HOLT INTEGRATED CIRCUITS
5
5 Page 
HI-8581
Vcc = 5V, V+=10V, V- = -10V, GND = 0V, TA = Oper. Temp. Range and fclk = 1MHz +0.1% with 60/40 duty cycle
PARAMETER
CONTROL WORD TIMING
SYMBOL
LIMITS
UNITS
MIN TYP MAX
Pulse Width - CWSTR
Setup - DATA BUS Valid to CWSTR HIGH
Hold - CWSTR HIGH to DATA BUS Hi-Z
RECEIVER TIMING
tCWSTR
tCWSET
tCWHLD
50
50
0
ns
ns
ns
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
Low Speed
Delay - D/R LOW to EN L0W
Delay - EN LOW to D/R HIGH
Setup - SEL to EN L0W
Hold - SEL to EN HIGH
Delay - EN L0W to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
FIFO TIMING
Pulse Width - EN1 or EN2
Spacing - EN HIGH to next EN L0W
tD/R
tD/R
tD/REN
tEND/R
tSELEN
tENSEL
tENDATA
tDATAEN
tEN
tENEN
0
0
0
50
80 50
50
16 µs
128 µs
ns
200 ns
ns
ns
80 ns
30 ns
ns
ns
Pulse Width - PL1 or PL2
Setup - DATA BUS Valid to PL HIGH
Hold - PL HIGH to DATA BUS Hi-Z
Spacing - PL1 or PL2
Delay - PL2 HIGH to TX/R LOW
TRANSMISSION TIMING
tPL
tDWSET
tDWHLD
tPL12
tTX/R
50
50
0
0
ns
ns
ns
ns
840 ns
Spacing - PL2 HIGH to ENTX HIGH
Delay - 32nd ARINC Bit to TX/R HIGH
Spacing - TX/R HIGH to ENTX L0W
LINE DRIVER OUTPUT TIMING
tPL2EN
tDTX/R
tENTX/R
0
0
µs
50 ns
ns
Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed
Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed
Line driver transition differential times:
(High Speed)
high to low
low to high
(Low Speed)
high to low
low to high
tENDAT
tENDAT
tfx
trx
tfx
trx
25 µs
200 µs
1.0 1.5 2.0 µs
1.0 1.5 2.0 µs
5.0 10 15 µs
5.0 10 15 µs
HOLT INTEGRATED CIRCUITS
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet HI-8581.PDF ] | |
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