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PDF ST10F168 Data sheet ( Hoja de datos )
| Número de pieza | ST10F168 | |
| Descripción | 16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST10F168
16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM
s HIGH PERFORMANCE CPU
– 16-BIT CPU WITH 4-STAGE PIPELINE
– 80ns INSTRUCTION CYCLE TIME AT 25MHz
CPU CLOCK
– 400ns 16 X 16-BIT MULTIPLICATION
– 800ns 32 / 16-BIT DIVISION
– ENHANCED BOOLEAN BIT MANIPULATION
FACILITIES
– ADDITIONAL INSTRUCTIONS TO SUPPORT
HLL AND OPERATING SYSTEMS
– SINGLE-CYCLE CONTEXT SWITCHING SUP-
PORT
s MEMORY ORGANIZATION
– 256K BYTE ON-CHIP FLASH MEMORY
– 10K ERASING / PROGRAMMING CYCLES
– UP TO 16M BYTE LINEAR ADDRESS SPACE
FOR CODE AND DATA (5M BYTE WITH CAN)
– 2K BYTE ON-CHIP INTERNAL RAM (IRAM)
– 6K BYTE ON-CHIP EXTENSION RAM (XRAM)
– 20 YEAR DATA RETENTION TIME
s FAST AND FLEXIBLE BUS
– PROGRAMMABLE EXTERNAL BUS CHARAC-
TE- RISTICS FOR DIFFERENT ADDRESS
RANGES
– 8-BIT OR 16-BIT EXTERNAL DATA BUS
– MULTIPLEXED OR DEMULTIPLEXED EXTER-
NAL ADDRESS / DATA BUSES
– FIVE PROGRAMMABLE CHIP-SELECT SIGNALS
– HOLD-ACKNOWLEDGE BUS ARBITRATION
SUPPORT
s INTERRUPT
– 8-CHANNEL PERIPHERAL EVENT CONTROL-
LER FOR SINGLE CYCLE, INTERRUPT DRIVEN
DATA TRANSFER
– 16-PRIORITY-LEVEL INTERRUPT SYSTEM
WITH 56 SOURCES, SAMPLE-RATE DOWN TO
40ns
s TIMERS
– TWO MULTI-FUNCTIONAL GENERAL PUR-
POSE TIMER UNITS WITH 5 TIMERS
– TWO 16-CHANNEL CAPTURE / COMPARE
UNITS.
s 4-CHANNEL PWM UNIT
s SERIAL CHANNELS
– SYNCHRONOUS / ASYNCHRONOUS SERIAL
CHANNEL
– HIGH-SPEED SYNCHRONOUS CHANNEL
PQFP144 (28 x 28 mm)
(Plastic Quad Flat Pack)
s A/D CONVERTER
– 16-CHANNEL 10-BIT
– 7.76µS CONVERSION TIME
s FAIL-SAFE PROTECTION
– PROGRAMMABLE WATCHDOG TIMER
– OSCILLATOR WATCHDOG
s ON-CHIP CAN 2.0B INTERFACE
s ON-CHIP BOOTSTRAP LOADER
s CLOCK GENERATION
– ON-CHIP PLL
– DIRECT OR PRESCALED CLOCK INPUT.
s UP TO 111 GENERAL PURPOSE I/O LINES
– INDIVIDUALLY PROGRAMMABLE AS INPUT,
OUTPUT OR SPECIAL FUNCTION.
– PROGRAMMABLE THRESHOLD (HYSTERESIS)
s IDLE AND POWER DOWN MODES
s SINGLE VOLTAGE SUPPLY: 5V ±10%
s 144-PIN PQFP PACKAGE
FLASH
CPU Core
PEC
Interrupt controller
RAM
Watchdog
OSC
P.0
P.1
P.4
P.6
P.5
BRG BRG
P.3 P.7
P.8
January 2002
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/74
1 page  
2 - PIN DATA
Figure 2 : Pin Configuration (top view)
P6.0/CS0
P6.1/CS1
P6.2/CS2
P6.3/CS3
P6.4/CS4
P6.5/HOLD
P6.6/HLDA
P6.7/BREQ
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P8.7/CC23IO
VDD
VSS
P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3
P7.4/CC28I0
P7.5/CC29I0
P7.6/CC30I0
P7.7/CC31I0
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
P5.8/AN8
P5.9/AN9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
ST10F168
ST10F168
108 P0H.0/AD8
107 P0L.7/AD7
106 P0L.6/AD6
105 P0L.5/AD5
104 P0L.4/AD4
103 P0L.3/AD3
102 P0L.2AD2
101 P0L.1/AD1
100 P0L.0/AD0
99 EA
98 ALE
97 READY
96 WR/WRL
95 RD
94 VSS
93 VDD
92 P4.7/A23
91 P4.6/A22/CAN_TxD
90 P4.5/A21/CAN_RxD
89 P4.4/A20
88 P4.3/A19
87 P4.2/A18
86 P4.1/A17
85 P4.0/A16
84 VPP/RPD
83 VSS
82 VDD
81 P3.15/CLKOUT
80 P3.13/SCLK
79 P3.12/BHE/WRH
78 P3.11/RXD0
77 P3.10/TXD0
76 P3.9/MTSR
75 P3.8/MRST
74 P3.7/T2IN
73 P3.6/T3IN
5/74
5 Page 
ST10F168
4 - MEMORY ORGANIZATION
The memory space of the ST10F168 is configured
in a Von Neumann architecture. Code memory,
data memory, registers and I/O ports are orga-
nized within the same linear address space of
16M Byte. The entire memory space can be
accessed bytewise or wordwise. Particular por-
tions of the on-chip memory have additionally
been made directly bit addressable.
FLASH: 256K Byte of on-chip Flash memory. See
Flash Memory on page 13
IRAM: 2K Byte of on-chip internal RAM
(dual-port) is provided as a storage for data, sys-
tem stack, general purpose register banks and
code. A register bank is 16 wordwide (R0 to R15)
and / or bytewide (RL0, RH0, …, RL7, RH7) gen-
eral purpose registers.
XRAM: 6K Byte of on-chip extension RAM (single
port XRAM) is provided as a storage for data, user
stack and code. The XRAM is connected to the
internal XBUS and is accessed like an external
memory in 16-bit demultiplexed bus-mode without
wait state or read / write delay (80ns access at
25MHz CPU clock). Byte and Word access are
allowed.
The XRAM address range is 00’D000h -
00’E7FFh if the XRAM is enabled (XPEN bit 2 of
SYSCON register). As the XRAM appears like
external memory, it cannot be used for the
ST10F168’s system stack or register banks. The
XRAM is not provided for single bit storage and
therefore is not bit addressable. If bit XPEN is
cleared, then any access in the address range
00’D000h - 00’E7FFh will be directed to external
memory interface, using the BUSCONx register
corresponding to address matching ADDRSELx
register.
SFR/ESFR: 1024 Byte (2 x 512 Byte) of address
space is reserved for the Special Function Regis-
ter areas. SFRs are wordwide registers which are
used for controlling and monitoring functions of
the different on-chip units.
CAN: Address range 00’EF00h - 00’EFFFh is
reserved for the CAN Module access. The CAN is
enabled by setting XPEN bit 2 of the SYSCON
register. Accesses to the CAN Module use demul-
tiplexed addresses and a 16-bit data bus (Byte
accesses are possible). Two wait states give an
access time of 160ns at 25MHz CPU clock. No
tristate wait state is used.
Note: If the CAN module is used, Port 4 can not
be programmed to output all 8 segment
address lines. Therefore, only 4 segment
address lines can be used, reducing the
external memory space to 5M Byte (1M
Byte per CS line)
To meet the needs of designs where more mem-
ory is required than is provided on chip, up to 16M
Byte of external RAM and / or ROM can be con-
nected to the microcontroller.
11/74
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ST10F168.PDF ] | |
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