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PDF UPD8086 Data sheet ( Hoja de datos )
| Número de pieza | UPD8086 | |
| Descripción | 16-Bit Microprocessor | |
| Fabricantes | NEC | |
| Logotipo |  |
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NEe Microcomputers, Inc.
16 BIT MICROPROCESSOR
NEe
JLPD8086
JLPD8086-2'"
DESC RIPT ION
The /lPD8086 is a 16-bit microprocessor that has both 8-bit and 16-bit attributes_ It
has a 16-bit wide physical path to memory for high performance. Its architecture
allows higher throughput than the 5 MHz /lPD8085A-2.
FEATU RES
• Can Directly Address 1 Megabyte of Memory
• Fourteen 16-Bit Registers with Symmetrical Operations
• Bit, Byte, Word, and Block Operations
• 8 and 16-Bit Signed and Unsigned Arithmetic Operations in Binary or Decimal
• Multiply and Divide Instructions
• 24 Operand Addressing Modes
• Assembly Language Compatible with the /lPD8080/8085
• Complet.e Family of Components for Design Flexibility
PIN CONFIGURATION
GND
AD14
AD13
AD12
ADll
AD10
AD9
ADB
AD7
ADS
AD5
AD4
AD3
AD2
ADl
ADO
NMI
INTR
elK
GND
Vee
AD15
A1S/S3
A17/S4
A1B/S5
A19/SS
SHE/S7
MN/MX
RD
HOLD
HlDA
iNA
M/iQ
DTIR
DEN
ALE
INTA
TEST
READY
RESET
(Fffi/GTIi)
(ROIGT1)
(C5CT<)
(82)
(S1)
(Sci)
(OSO)
(OSl)
II
*Preliminary
411
1 page  
~PD8086
AC CHARACTERISTICS
MINIMUM COMPLEXITY
SYSTEM
PARAMETER
elK Cycle Period -IlPDB086
elK low Time
eLK High Time
eLK Rise Time
elK Fall Time
Data In Setup Time
Data In Hold Time
ROY Setup Time into /lPD8284
Q)@
ROY Hold Time into /.IP08284
,Q)@
READY Setup Time ,nto j.lPD8086
READY Hold Time into J.!PD8086
READY Inactive to elK
@
HOLD Setup Time
INTR, NMl, TEST Setup Time
@
SYMBOL
TCLCL
TeLCH
TCHCL
TCH1CH2
TCL2Cll
reVel
TelDX
TR1VCL
TeLA1 x
TRYHCH
TCHAYX
TRYLCL
THVCH
TINVCH
TIMING REQUIREMENTS
}.JPD8086
J.lPDB086-2 (Preliminary I
MIN MAX MIN MAX
200
(2/3 TCLCLl-15
(1/3 TClCLi +2
30
10
15
500
10
10
125 500
(2/3 reLell -15
(1/3 reLeLl +2
10
10
20
10
35
(2/3 TCLCLl-15
30
-8
35
30
(2/3 TCLCL)-15
20
-8
20
15
UNITS
TEST
CONDITIONS
From 1.0V to 3,SV
From 3.SV to 1.0V
TIMING RESPONSES
PARAMETER
SYMBOL
TIMING RESPONSES
IlPDS086
>,PD8OB6-2 (Preliminary I
MIN MAX MIN MAX
UNITS
TEST
CONDITIONS
Address Valid Delay
Address Hold Time
Addre~ Float Delay
ALE Width
ALE Active Delay
ALE Inactive Delay
Address Hold Time to ALE Inactive
Data Valid Delay
Data Hold Time
Data Hold Time After WR
Control Active Delay 1
Control Active Delay 2
Control Active Delay
Address Float to READ Active
RDActive Oelay
AD Inactive Delay
RD Inactive to Next Address Active
HLOA Valid Delay
FlDWldth
WRWldth
Address Valid to ALE La.....
TCLAV
TCLAX
TCLAZ
TLHLL
TCLLH
TCHLL
TLLAX
TCLDV
TCHDX
TWHDX
TCVCTV
TCHCTV
TCVCTX
TAZRL
TCLRL
TCLAH
TAHAV
TCLHAV
TRLRH
TWLWH
TAVAL
10
10
TCLAX
TCLCH-20
TCHCL-l0
10
10
TCLCH-30
10
10
10
110
80
80
85
110
110
110
110
10
10
TCLCL-45
10
2TCLCL-75
2TCLCL-60
TCLCH-60
165
150
160
10
10
TCLAX
TCLCH-1O
TCHCL-l0
10
10
TCLCH-30
10
10
10
60
50
50
55
60
70
60
70
10
10
TCLCL-4Q
10
)TCLCl-50
2TCLCL-40
TCLCH-40
100
80
100
"'
CL = 20-100 pF tor
all ,uPD8086 Outputs
(In addition to
",PD9086 self-load)
CDNOTES:
Signal at ",PD8284 sho.....n for reference only
@ Setup requirement for asynchronous signal only to guarantee recognition at next ClK.
@ Applies only to T2 stata. (8 ns into T3)
II
415
5 Page 
ASYNCHRONOUS SIGNAL
RECOGNITION
NMI
INTR
SIGNAL \.:_ _ __
p.PD8086
CDNOTE:
Setup requirements for asynchronous signals only to guarantee recognition
at next eLK.
BUS LOCK SIGNAL TIMING
REQUEST/GRANT SEQUENCE
TIMING*
A016-ADO 1>------------<1 :
> - - - - - - - - - - - - - <A18/Se-Ale/S3
w.-~
>-_ _ _ _..J
8HE1S7
COPROCESSOR
(j)
CDNOTE:
The coprocessor may not drive the buses outside the region shown without
rjsking contention.
*for Maximum Mode only
421
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet UPD8086.PDF ] | |
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