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PDF IN74LV573 Data sheet ( Hoja de datos )
| Número de pieza | IN74LV573 | |
| Descripción | Octal Transparent Latch | |
| Fabricantes | IK Semiconductor | |
| Logotipo |  |
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TECHNICAL DATA
Octal D-type transparent latch (3-State)
IN74LV573
The 74LV573 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT573.
The 74LV573 is an octal D-type transparent latch featuring separate D-
type inputs for each latch and 3-State outputs for bus oriented applications.
A latch enable (LE) input and an output enable (OE) input are common to
all internal latches.
The ‘573’ consists of eight D-type transparent latches with 3-State true
outputs. When LE is HIGH, data at the D n inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output will change each
time its corresponding D-input changes.
When LE is LOW the latches store the information that was present at
the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the eight latches are available at the
outputs. When OE is HIGH, the outputs go to the high impedance OFF-
state. Operation of the OE input does not affect the state of the latches.
The ‘573’ is functionally identical to the ‘563’ and the ‘373’, but the
‘563’ has inverted outputs and the ‘373’ has a different pin arrangement.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
• Supply voltage range: 1.0 to 5.5 V
• Low input current: 1.0 µА; 0.1 µА at Т = 25 °С
• High Noise Immunity Characteristic of CMOS Devices
N SUFFIX
PLASTIC DIP
20
1
20
1
DW SUFFIX
SO
ORDERING INFORMATION
IN74LV573N
Plastic DIP
IN74LV573DW
SOIC
TA = -40° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheet4uP.PIcNINo102m0==GVNCCD
FUNCTION TABLE
Output
Enable
L
L
L
Inputs
Clock
L,H,
D
H
L
X
HX
H= high level
L = low level
X = don’t care
Z = high impedance
X
Output
Q
H
L
no
change
Z
1
1 page  
IN74LV573
TIMING REQUIREMENTS (CL=50 pF, tr=tf=2.5 ns)
Symbol
Parameter
tw Pulse Width, LE (low or
high)
tsu Setup Time, Data to LE
th Hold Time, LE to Data
Test
conditions
VI = 0 V or V1
Figures 1,3
VI = 0 V or V1
Figures 1,5
VI = 0 V or V1
Figures 1,5
VCC Guaranteed Limit
V -40°C to 25°C 85°C
125°C
min max min max min max
1.2 100 - 125
150
2.0 29 - 34 - 41 -
2.7 21 - 25 - 30 -
3.0 17 - 20 - 24 -
4.5 15 - 18 - 21 -
1.2 50 - 75
100
2.0 15 - 17 - 20 -
2.7 11 - 13 - 15 -
3.0 8
- 10 - 12
-
4.5 6 - 8
10
1.2 40 - 40 - 40 -
2.0 8 - 8 - 8 -
2.7 8 - 8 - 8 -
3.0 8 - 8 - 8 -
4.5 8 - 8 - 8 -
Unit
ns
ns
ns
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
1k
CL*
Connect to VCC when
testing tPLZ and tPZL
Connect to GND when
testing tPHZ and tPZH
* Includes all probe and jig capacitance
Figure 1. Test Circuit
* Includes all probe and jig capacitance
Figure 2. Test Circuit
Figure 3. Switching Waveforms
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet IN74LV573.PDF ] | |
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