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PDF IN74LV174 Data sheet ( Hoja de datos )

Número de pieza IN74LV174
Descripción Hex D-Type Flip-Flop
Fabricantes IK Semiconductor 
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No Preview Available ! IN74LV174 Hoja de datos, Descripción, Manual

TECHNICAL DATA
Hex D-type flip-flop with reset; positive edge-trigger
IN74LV174
The 74LV174 is a low–voltage Si–gate CMOS device and is pin and
function compatible with the 74HC/HCT174.
The 74LV174 has six edge–triggered D–type flip–flops with individual D
inputs and Q outputs. The common clock (CP) and master reset (MR)
inputs load and reset (clear) all flip–flops simultaneously.
The register is fully edge–triggered. The state of each D input, one set–up
time prior to the LOW–to–HIGH clock transition, is transferred to the
corresponding output of the flip–flop.
A LOW level on the MR input forces all outputs LOW, independently of
clock or data inputs.
The device is useful for applications requiring true outputs only and clock
and master reset inputs that are common to all storage elements.
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
Supply voltage range: 1.2 to 5.5 V
Low input current: 1.0 µА; 0.1 µА at Т = 25 °С
Output current: 6 mA at Vcc = 3.0 V; 12 mA at Vcc = 4.5 V
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
ORDERING INFORMATION
IN74LV174N Plastic
IN74LV174D SOIC
TA = -40° to 125° C for all packages
PIN ASSIGNMENT
MR
Q0
D0
D1
Q1
D2
Q2
GND
1
2
3
4
5
6
7
8
16 V CC
15 Q5
14 D5
13 D4
12 Q4
11 D3
10 Q3
9 CP
CP
MR
www.datasheet4PuPINI.N0c81o6==mGVNCCD
FUNCTION TABLE
Inputs
MR CP
LX
H
H
HL
H
H= high level
L = low level
X = don’t care
Outputs
Dn Qn
XL
HH
LL
X no change
X no change
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IN74LV174 pdf
IN74LV174
tr
CP
10%
VM(1)
90%
tf
tw
1/fmax
tPLH
Q VM(1)
V1(2)
GND
t PHL
VOH
VOL
MR
t PHL
Q
tw
VM(1)
VM(1)
CP
t rec
V
(1)
M
V1(2)
GND
VOH
VOL
V1(2)
GND
Figure 1. Switching Waveforms
DATA
CP
VM (1)
VALID
tsu th
VM (1)
V1(2)
GND
V1(2)
GND
Figure 2. Switching Waveforms
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
RL
CL*
Figure 3. Switching Waveforms
* Includes all probe and jig capacitance
Figure 4. Test Circuit
Note:
(1) VM = 1.5 V at VCC = 2.7 V
VM = 0.5 VCC at VCC =1.2 V, 2.0 V, 3.0 V, 4.5 V
(2) V1 = VCC at VCC =1.2 V, 2.0 V, 2.7 V, 4.5 V
V1 = 2.7 V at VCC = 3.0 V
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