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IN74LV74 の電気的特性と機能

IN74LV74のメーカーはIK Semiconductorです、この部品の機能は「Dual D-Type Flip-Flop」です。


製品の詳細 ( Datasheet PDF )

部品番号 IN74LV74
部品説明 Dual D-Type Flip-Flop
メーカ IK Semiconductor
ロゴ IK Semiconductor ロゴ 




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IN74LV74 Datasheet, IN74LV74 PDF,ピン配置, 機能
TECHNICAL DATA
IN74LV74
Dual D-type flip-flop with set and reset;
positive-edge trigger
The IN74LV74 is a low-voltage Si-gate CMOS device and is pin
and function compatible with 74HC/HCT74.
The IN74LV74 is a dual positive edge triggered, D-type flip-flop
with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD)
inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable one set-up time prior to the LOW-to-
HIGH clock transition, for predictable operation. Schmitt-trigger action
in the clock input makes the circuit highly tolerant to slower clock rise
and fall times.
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
Supply voltage range: 1.2 to 3.6 V
Low input current: 1.0 µА; 0.1 µА at Т = 25 °С
High Noise Immunity Characteristic of CMOS Devices
N SUFFIX
PLASTIC
14
1
D SUFFIX
14
1
SOIC
ORDERING INFORMATION
IN74LV74N Plastic
IN74LV74D SOIC
TA = -40° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
RESET 1 1
DATA 1 2
CLOCK 1 3
SET 1 4
Q1 5
Q1 6
GND 7
14 V CC
13 RESET 2
12 DATA2
11 CLOCK 2
10 SET 2
9 Q2
8 Q2
www.datasheet4PuPINI.Nc102o0==mGVNCCD
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock Data Q
Q
LH X XHL
HL X XLH
L L X X H* H*
HH
HHL
HH
LLH
H H L X No Change
H H H X No Change
HH
X No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredictable
if Set and Reset go high simultaneously.
H= high level
L = low level
X = don’t care
Z = high impedance
1

1 Page





IN74LV74 pdf, ピン配列
IN74LV74
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Test
VCC
Guaranteed Limit
Symbol Parameter
conditions
V
25°C -40°C to 85°C
125°C
VIH HIGH level input
voltage
min max min max min max
1.2 0.9 - 0.9
-
0.9
-
2.0 1.4 - 1.4
-
1.4
-
3.0 2.1 - 2.1
-
2.1
-
3.6 2.5 - 2.5
-
2.5
-
VIL LOW level output
voltage
1.2 - 0.3 -
0.3
-
0.3
2.0 - 0.6 -
0.6
-
0.6
3.0 - 0.9 -
0.9
-
0.9
3.6 - 1.1 -
1.1
-
1.1
VOH HIGH level output VI = VIH or VIL 1.2 1.1 - 1.0
-
1.0
-
voltage
IO = -50 µА
2.0 1.92 - 1.9
-
1.9
-
3.0 2.92 - 2.9
-
2.9
-
3.6 3.52 - 3.5
-
3.5
-
VI = VIH or VIL
3.0 2.48 - 2.34
-
2.20
-
IO = -6mА
VOL LOW level output VI = VIH or VIL 1.2 - 0.09 -
0.1
-
0.1
voltage
IO = 50 µА
2.0 - 0.09 -
0.1
-
0.1
3.0 - 0.09 -
0.1
-
0.1
3.6 - 0.09 -
0.1
-
0.1
VI = VIH or VIL 3.0 - 0.33 -
0.4
-
0.5
IO = 6 mА
II Input current
VI = VCC or 0 V
*
- ±0.1 - ±1.0
-
±1.0
ICC Supply current
VI =VCC or 0 V * - 4.0 -
40
-
80
IO = 0 µА
* VCC = 3.3 ± 0.3 V
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tr=tf=6.0 ns)
Test
VCC
Guaranteed Limit
Symbol
Parameter
conditions V
25°C -40°C to 85°C
125°C
min max min max min
tPHL, tPLH Propagation delay , Clock VI = 0 V or VCC 1.2 - 140 - 160 -
to Q or Q
Figures 1,3
2.0 - 45 - 56 -
* - 28 - 35 -
max
180
67
42
tPHL, tPLH Propagation delay , Set to VI = 0 V or VCC 1.2 - 150 - 170 -
Q or Q
Figures 2,3
2.0 - 44 - 54 -
* - 27 - 34 -
190
65
41
tPHL, tPLH Propagation delay , Reset VI = 0 V or VCC 1.2 - 160 - 180 -
to Q or Q
Figures 2,3
2.0 - 47 - 58 -
* - 29 - 37 -
200
70
44
tTHL, tTLH Output Transition Time, VI = 0 V or VCC 1.2 - 90 - 110 -
Any Output
Figures 1,3
2.0 - 20 - 25 -
* - 15 - 19 -
130
30
23
CI Input capacitance
3.0 - 7.0 - - -
CPD Power dissipation
VI = 0 V or VCC
capacitance (per flip-flop)
- 48 - - -
-
-
Unit
V
V
V
V
V
V
µА
µА
Unit
ns
ns
ns
ns
pF
pF
3


3Pages


IN74LV74 電子部品, 半導体
N SUFFIX PLASTIC DIP
(MS - 001AA)
A
14
1
8
B
7
FL
C
-T- SEATING
N PLANE
G
KM
D
H
NOTES:
0.25 (0.010) M T
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
J
IN74LV74
Symbol
A
B
C
D
F
G
H
J
K
L
M
N
Dimension, mm
MIN
18.67
MAX
19.69
6.1 7.11
5.33
0.36 0.56
1.14 1.78
2.54
7.62
0° 10°
2.92 3.81
7.62 8.26
0.2 0.36
0.38
D SUFFIX SOIC
(MS - 012AB)
A
14 8
H BP
1G
7
C
R x 45
-T-
D
NOTES:
K
0.25 (0.010) M T C M
SEATING
PLANE
J
F
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B 0.25 mm (0.010) per side.
Symbol
A
B
C
D
F
G
H
MJ
K
M
P
R
Dimension, mm
MIN MAX
8.55 8.75
3.8 4
1.35 1.75
0.33 0.51
0.4 1.27
1.27
5.27
0° 8°
0.1 0.25
0.19 0.25
5.8 6.2
0.25 0.5
6

6 Page



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部品番号部品説明メーカ
IN74LV74

Dual D-Type Flip-Flop

IK Semiconductor
IK Semiconductor


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