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ADSP-21065L の電気的特性と機能

ADSP-21065LのメーカーはAnalog Devicesです、この部品の機能は「Low-cost Sharc / 60 Mhz / 180 Mflops / 3.3v / Floating Point」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADSP-21065L
部品説明 Low-cost Sharc / 60 Mhz / 180 Mflops / 3.3v / Floating Point
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADSP-21065L Datasheet, ADSP-21065L PDF,ピン配置, 機能
a
DSP Microcomputer
ADSP-21065L
SUMMARY
High Performance Signal Computer for Communica-
tions, Audio, Automotive, Instrumentation and
Industrial Applications
Super Harvard Architecture Computer (SHARC®)
Four Independent Buses for Dual Data, Instruction,
and I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
544 Kbits On-Chip SRAM Memory and Integrated I/O
Peripheral
I2S Support, for Eight Simultaneous Receive and Trans-
mit Channels
KEY FEATURES
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
Two External Port, DMA Channels and Eight Serial
Port, DMA Channels
SDRAM Controller for Glueless Interface to Low Cost
External Memory (@ 66 MHz)
64M Words External Address Range
12 Programmable I/O Pins and Two Timers with Event
Capture Options
Code-Compatible with ADSP-2106x Family
208-Lead MQFP or 196-Ball Mini-BGA Package
3.3 Volt Operation
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE
Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with Dual 80-Bit Accumulators
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT But-
terfly Computation
1024-Point Complex FFT Benchmark: 0.274 ms (18,221
Cycles)
CORE PROCESSOR
INSTRUCTION
CACHE
32 ؋ 48 BIT
DAG1
DAG2
8 ؋ 4 ؋ 32 8 ؋ 4 ؋ 24
PROGRAM
SEQUENCER
24 PM ADDRESS BUS
32 DM ADDRESS BUS
BUS
CONNECT
(PX)
48 PM DATA BUS
40 DM DATA BUS
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
ADDR
DATA
ADDR
DATA
I/O PORT
DATA
ADDR
ADDR
DATA
IOA IOD
17 48
JTAG
TEST &
EMULATION
7
EXTERNAL
PORT
SDRAM
INTERFACE
ADDR BUS
MUX
24
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
32
HOST PORT
t4u.comMULTIPLIER
DATA
REGISTER
FILE
16 ؋ 40 BIT
BARREL
SHIFTER
ALU
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS, TIMER
&
DATA BUFFERS
DMA
CONTROLLER
SPORT 0
SPORT 1
I/O PROCESSOR
Figure 1. Functional Block Diagram
eeSHARC is a registered trademark of Analog Devices, Inc.
4
(2 Rx, 2Tx)
(I2S)
(2 Rx, 2Tx)
(I2S)
shREV. B
taInformation furnished by Analog Devices is believed to be accurate and
areliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
.dwhich may result from its use. No license is granted by implication or
wwwotherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000

1 Page





ADSP-21065L pdf, ピン配列
ADSP-21065L
GENERAL DESCRIPTION
The ADSP-21065L is a powerful member of the SHARC
family of 32-bit processors optimized for cost sensitive appli-
cations. The SHARC—Super Harvard Architecture—offers the
highest levels of performance and memory integration of any
32-bit DSP in the industry—they are also the only DSP in the
industry that offer both fixed and floating-point capabilities,
without compromising precision or performance.
Fabricated in a high speed, low power CMOS process, 0.35 µm
technology, the ADSP-21065L offers the highest performance
by a 32-bit DSP—66 MIPS (198 MFLOPS). With its on-chip
instruction cache, the processor can execute every instruction in
a single cycle. Table I lists the performance benchmarks for the
ADSP-21065L.
The ADSP-21065L SHARC combines a floating-point DSP
core with integrated, on-chip system features, including a
544 Kbit SRAM memory, host processor interface, DMA con-
troller, SDRAM controller, and enhanced serial ports.
Figure 1 shows a block diagram of the ADSP-21065L, illustrat-
ing the following architectural features:
Computation Units (ALU, Multiplier, and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Timers with Event Capture Modes
On-Chip, dual-ported SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port and SDRAM Interface
DMA Controller
Enhanced Serial Ports
JTAG Test Access Port
Table I. Performance Benchmarks
Benchmark
Cycle Time
1024-Pt. Complex FFT
(Radix 4, with Digit Reverse)
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
FIR Filter (per Tap)
IIR Filter (per Biquad)
Divide Y/X
Inverse Square Root (1/x)
DMA Transfers
Timing
15.00 ns
Cycles
1
0.274 ns
18221
135 ns
240 ns
15 ns
60 ns
90 ns
135 ns
264 Mbytes/sec.
9
16
1
4
6
9
ADSP-21000 FAMILY CORE ARCHITECTURE
The ADSP-21065L is code and function compatible with the
ADSP-21060/ADSP-21061/ADSP-21062. The ADSP-21065L
includes the following architectural features of the SHARC
family core.
CLOCK
RESET
01
ADSP-21065L
#1
CLKIN
RESET
ID1-0
ADDR23-0
SPORT0 DATA31-0
TX0_A
TX0_B
RD
WR
RX0_A
RX0_B
SPORT1
TX1_A
TX1_B
ACK
MS3-0
BMS
SBTS
SW
CS
RX1_A
RX1_B
HBR
HBG
REDY
CONTROL
RAS
CAS
DQM
SDWE
SDCLK1-0
SDCKE
SDA10
CPA
BR2
BR1
CS BOOT
ADDR EPROM
DATA (OPTIONAL)
HOST
PROCESSOR
(OPTIONAL)
CS
ADDR
DATA
ADDR
DATA
CS SDRAM
(OPTIONAL)
RAS
CAS
DQM
WE
CLK
CKE
A10
Figure 2. ADSP-21065L Single-Processor System
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier, and shifter all
perform single-cycle instructions. The three units are arranged
in parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier
operations. These computation units support IEEE 32-bit
single-precision floating-point, extended precision 40-bit floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 pri-
mary, 16 secondary) register file, combined with the ADSP-
21000 Harvard architecture, allows unconstrained data flow
between computation units and internal memory.
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-21065L features an enhanced Super Harvard Archi-
tecture in which the data memory (DM) bus transfers data and
the program memory (PM) bus transfers both instructions and
data (see Figure 1). With its separate program and data memory
buses, and on-chip instruction cache, the processor can simulta-
neously fetch two operands and an instruction (from the cache),
all in a single cycle.
Instruction Cache
The ADSP-21065L includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions that
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular Buffers
The ADSP-21065L’s two data address generators (DAGs)
implement circular data buffers in hardware. Circular buffers
allow efficient programming of delay lines and other data
REV. B
–3–


3Pages


ADSP-21065L 電子部品, 半導体
ADSP-21065L
ADSP-21065L
#2
CLKIN
ADDR23-0
RESET
DATA31-0
10
CLOCK
RESET
01
ID1-0
CONTROL
SPORT0
SPORT1
CPA
BR2
BR1
ADSP-21065L
#1
CLKIN
RESET
ID1-0
ADDR23-0
DATA31-0
SPORT0
RD
WR
SPORT1
CONTROL
ACK
MS3-0
BMS
SBTS
SW
CS
HBR
HBG
REDY
RAS
CAS
DQM
SDWE
SDCLK1-0
SDCKE
SDA10
CPA
BR2
BR1
CS BOOT
ADDR
DATA
EPROM
(OPTIONAL)
HOST
PROCESSOR
(OPTIONAL)
CS
ADDR
DATA
ADDR
DATA
CS SDRAM
(OPTIONAL)
RAS
CAS
DQM
WE
CLK
CKE
A10
Figure 3. Multiprocessing System
–6– REV. B

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
ADSP-21065

DSP Microcomputer

Analog Devices
Analog Devices
ADSP-21065L

DSP Microcomputer

Analog Devices
Analog Devices
ADSP-21065L

Low-cost Sharc / 60 Mhz / 180 Mflops / 3.3v / Floating Point

Analog Devices
Analog Devices
ADSP-21065LCS-240

DSP Microcomputer

Analog Devices
Analog Devices


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