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IN74ACT112のメーカーはIK Semiconductorです、この部品の機能は「Dual J-K Negative-Edge-Triggered Flip-Flop」です。 |
部品番号 | IN74ACT112 |
| |
部品説明 | Dual J-K Negative-Edge-Triggered Flip-Flop | ||
メーカ | IK Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとIN74ACT112ダウンロード(pdfファイル)リンクがあります。 Total 6 pages
TECHNICAL DATA
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
IN74ACT112
The IN74ACT112 is identical in pinout to the LS/ALS112,
HC/HCT112. The IN74ACT112 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74ACT112N Plastic
IN74ACT112D SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheetPP4IINNu81.=6c=GVoNCDCm
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K Q
Q
LH
X XX H L
HL
LL
X XX L H
X X X L* L*
HH
L L No Change
HH
LH L
H
HH
HL H
L
HH
HH
Toggle
HH
L X X No Change
HH
H X X No Change
HH
X X No Change
* Both outputs will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
1
1 Page IN74ACT112
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VCC
V
VIH Minimum High-
VOUT=0.1 V or VCC - 0.1 V 4.5
Level Input Voltage
5.5
VIL Maximum Low -
VOUT=0.1 V or VCC - 0.1 V 4.5
Level Input Voltage
5.5
VOH Minimum High-
IOUT ≤ -50 µA
Level Output Voltage
*VIN= VIL or VIH
IOH=-24 mA
IOH=-24 mA
VOL Maximum Low-
IOUT ≤ 50 µA
Level Output Voltage
*VIN= VIL or VIH
IOL=24 mA
IOL=24 mA
IIN Maximum Input
Leakage Current
VIN=VCC or GND
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
∆ICCT
IOLD
Additional Max
ICC/Input
+Minimum Dynamic
Output Current
VIN=VCC - 2.1 V
VOLD=1.65 V Max
5.5
5.5
IOHD +Minimum Dynamic VOHD=3.85 V Min
Output Current
5.5
ICC Maximum Quiescent VIN=VCC or GND
Supply Current
(per Package)
5.5
* All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Guaranteed Limits
25 °C
-40°C to
85°C
2.0 2.0
2.0 2.0
0.8 0.8
0.8 0.8
4.4 4.4
5.4 5.4
3.86 3.76
4.86 4.76
0.1 0.1
0.1 0.1
0.36 0.44
0.36 0.44
±0.1 ±1.0
1.5
75
-75
4.0 40
Unit
V
V
V
V
µA
mA
mA
mA
µA
3
3Pages IN74ACT112
N SUFFIX PLASTIC DIP
(MS - 001BB)
A
16 9
B
18
FL
C
-T- SEATING
PLANE
N
G
KM
D
H
NOTES:
0.25 (0.010) M T
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
J
Symbol
A
B
C
D
F
G
H
J
K
L
M
N
Dimension, mm
MIN MAX
18.67 19.69
6.1 7.11
5.33
0.36 0.56
1.14 1.78
2.54
7.62
0° 10°
2.92 3.81
7.62 8.26
0.2 0.36
0.38
D SUFFIX SOIC
(MS - 012AC)
A
16 9
H BP
1G
8
C
R x 45
-T-
D
SEATING
K PLANE
0.25 (0.010) M T C M
J
F
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
Symbol
A
B
C
D
F
G
MH
J
K
M
P
R
Dimension, mm
MIN MAX
9.8 10
3.8 4
1.35 1.75
0.33 0.51
0.4 1.27
1.27
5.72
0° 8°
0.1 0.25
0.19 0.25
5.8 6.2
0.25 0.5
6
6 Page | |||
ページ | 合計 : 6 ページ | ||
|
PDF ダウンロード | [ IN74ACT112 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
IN74ACT11 | Triple 3-Input AND Gate | IK Semiconductor |
IN74ACT112 | Dual J-K Negative-Edge-Triggered Flip-Flop | IK Semiconductor |