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IN74ACT652 の電気的特性と機能

IN74ACT652のメーカーはIK Semiconductorです、この部品の機能は「Octal Bus Transceiver/Register」です。


製品の詳細 ( Datasheet PDF )

部品番号 IN74ACT652
部品説明 Octal Bus Transceiver/Register
メーカ IK Semiconductor
ロゴ IK Semiconductor ロゴ 




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IN74ACT652 Datasheet, IN74ACT652 PDF,ピン配置, 機能
TECHNICAL DATA
Octal 3-State Bus Transceivers
and D Flip-Flops
High-Speed Silicon-Gate CMOS
IN74ACT652
The IN74ACT652 is identical in pinout to the LS/ALS652,
HC/HCT652. The IN74ACT652 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
These devices consists of bus transceiver circuits, D-type flip-flop,
and control circuitry arranged for multiplex transmission of data directly
from the data bus or from the internal storage registers. Direction and
Output Enable are provided to select the read-time or stored data function.
Data on the A or B Data bus, or both, can be stored in the internal D flip-
flops by low-to-high transitions at the appropriate clock pins (A-to-B
Clock or B-to-A Clock) regardless of the select or enable or enable
control pins. When A-to-B Source and B-to-A Source are in the real-time
transfer mode, it is also possible to store data without using the internal
D-type flip-flops by simultaneously enabling Direction and Output
Enable. In this configuration each output reinforces its input. Thus, when
all other data sources to the two sets of bus lines are at high impedance,
each set of bus lines will remain at its last state.
The IN74ACT652 has noninverted outputs.
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74ACT652N Plastic
IN74ACT652DW SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheet4u.comPPININ1224==GVNCCD
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IN74ACT652 pdf, ピン配列
IN74ACT652
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VCC
V
VIH Minimum High-
VOUT=0.1 V or VCC-0.1 V
Level Input Voltage
4.5
5.5
VIL Maximum Low -
VOUT=0.1 V or VCC-0.1 V
Level Input Voltage
4.5
5.5
VOH Minimum High-
IOUT -50 µA
Level Output Voltage
*VIN=VIH or VIL
IOH=-24 mA
IOH=-24 mA
VOL Maximum Low-
IOUT 50 µA
Level Output Voltage
*VIN=VIH or VIL
IOL=24 mA
IOL=24 mA
IIN Maximum Input
Leakage Current
VIN=VCC or GND
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
ICCT
IOZ
IOLD
Additional Max.
ICC/Input
Maximum Three-
State Leakage
Current
+Minimum Dynamic
Output Current
VIN=VCC - 2.1 V
VIN(OE)= VIH or VIL
VIN =VCC or GND
VOUT =VCC or GND
VOLD=1.65 V Max
5.5
5.5
5.5
IOHD +Minimum Dynamic VOHD=3.85 V Min
Output Current
5.5
ICC Maximum Quiescent VIN=VCC or GND
Supply Current
(per Package)
5.5
* All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Guaranteed Limits
25 °C
-40°C to
85°C
2.0 2.0
2.0 2.0
0.8 0.8
0.8 0.8
4.4 4.4
5.4 5.4
3.86 3.76
4.86 4.76
0.1 0.1
0.1 0.1
0.36 0.44
0.36 0.44
±0.1 ±1.0
1.5
±0.6 ±6.0
75
-75
8.0 80
Unit
V
V
V
V
µA
mA
µA
mA
mA
µA
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IN74ACT652 電子部品, 半導体
IN74ACT652
FUNCTION TABLE
Dir. OE CAB CBA SAB SBA
A
B
FUNCTION
INPUTS INPUTS Both the A bus and the B bus are inputs.
L HXXXX
Z
Z The output functions of the A and B bus
are disabled.
X X INPUTS INPUTS Both the A and B bus are used for inputs
to the internal flip-flops. Data at the bus
will be stored on low to high transition of
the clock inputs.
OUTPUTS INPUTS The A bus are outputs and the B bus are
inputs.
X* X X L
L
H
L The data at the B bus are displayed at the
H A bus.
L L X*
XL
L
H
L The data at the B bus are displayed at the
H A bus. The data of the B bus are stored to
the internal flip-flops on low to high
transition of the clock pulse.
X* X X H
Qn
X The data stored to the internal flip-flops,
are displayed at the A bus.
X*
XH
H
H The data at the B bus are stored to the
L L internal flip-flops on low to high
transition of the clock pulse. The states of
the internal flip-flops output directly to
the A bus.
INPUTS OUTPUTS The A bus are inputs and the B bus are
outputs.
X X* L X
L
H
L The data at the A bus are displayed at the
H B bus.
HH
X* L X
L
H
L The data at the B bus are displayed at the
H A bus. The data of the B bus are stored to
the internal flip-flops on low to high
transition of the clock pulse.
X X* H X
X
Qn The data stored to the internal flip-flops
are displayed at the B bus.
X* H X
L
H
L The data at the A bus are stored to the
H internal flip-flops on low to high
transition of the clock pulse. The states of
the internal flip-flops output directly to
the B bus.
OUTPUTS OUTPUTS Both the A bus and the B bus are outputs
H LXXHH
Qn
Qn The data stored to the internal flip-flops
are displayed at the A and B bus
respectively.
HH
Qn
Qn The output at the A bus are displayed at
the B bus, the output at the B bus are
displayed at the A bus respec.
X : DON’T CARE
Z : HIGH IMPEDANCE
Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION
OF THE CLOCK INPUTS
* : THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW
TO TRANSITION OF THE CLOCK INPUTS
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部品番号部品説明メーカ
IN74ACT651

Octal Bus Transceiver/Register

IK Semiconductor
IK Semiconductor
IN74ACT652

Octal Bus Transceiver/Register

IK Semiconductor
IK Semiconductor


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