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PDF IN74AC112 Data sheet ( Hoja de datos )

Número de pieza IN74AC112
Descripción Dual J-K Negative-Edge-Triggered Flip-Flop
Fabricantes IK Semiconductor 
Logotipo IK Semiconductor Logotipo



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No Preview Available ! IN74AC112 Hoja de datos, Descripción, Manual

TECHNICAL DATA
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
IN74AC112
The IN74AC112 is identical in pinout to the LS/ALS112,
HC/HCT112. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS outputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
High Noise Immunity Characteristic of CMOS Devices
Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74AC112N Plastic
IN74AC112D SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheetPP4IINNu81.=6c=GVoNCDCm
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K Q
Q
LH
X XX H L
HL
LL
X XX L H
X X X L* L*
HH
L L No Change
HH
LH L
H
HH
HL H
L
HH
HH
Toggle
HH
L X X No Change
HH
H X X No Change
HH
X X No Change
* Both outputs will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
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IN74AC112 pdf
IN74AC112
Figure 1. Switching Waveform
Figure 2. Switching Waveform
Figure 3. Switching Waveform
EXPANDED LOGIC DIAGRAM
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