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IN74AC109 の電気的特性と機能

IN74AC109のメーカーはIK Semiconductorです、この部品の機能は「Dual J-K Positive-Edge-Triggered Flip-Flop」です。


製品の詳細 ( Datasheet PDF )

部品番号 IN74AC109
部品説明 Dual J-K Positive-Edge-Triggered Flip-Flop
メーカ IK Semiconductor
ロゴ IK Semiconductor ロゴ 




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IN74AC109 Datasheet, IN74AC109 PDF,ピン配置, 機能
TECHNICAL DATA
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
IN74AC109
The IN74AC109 is identical in pinout to the LS/ALS109,HC/HCT109.
The device inputs are compatible with standard CMOS outputs, with
pullup resistors, they are compatible with LS/ALS outputs.
This device consists of two J-K flip-flops with individual set, reset,
and clock inputs. Changes at the inputs are reflected at the outputs with
the next low-to-high transition of the clock. Both Q to Q outputs are
available from each flip-flop.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
High Noise Immunity Characteristic of CMOS Devices
Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74AC109N Plastic
IN74AC109D SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheet4uPPI.INNc81o=6=mGVNCDC
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K Q Q
LH
X XX H L
HL
LL
X XX L H
X
X X H*
H*
HH
LL L H
HH
H L Toggle
HH
L H No Change
HH
HH H L
HH
L X X No Change
X = Don’t care
*Both outputs will remain high as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
1

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IN74AC109 pdf, ピン配列
IN74AC109
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VCC Guaranteed Limit
V 25 °C -40°C to
85°C
VIH Minimum High-
VOUT=0.1 V or VCC-0.1 V
Level Input Voltage
3.0 2.1
4.5 3.15
5.5 3.85
2.1
3.15
3.85
VIL Maximum Low -
VOUT=0.1 V or VCC-0.1 V
Level Input Voltage
3.0 0.9
4.5 1.35
5.5 1.65
0.9
1.35
1.65
VOH Minimum High-
IOUT -50 µA
Level Output Voltage
*VIN=VIH or VIL
IOH=-12 mA
IOH=-24 mA
IOH=-24 mA
VOL Maximum Low-
IOUT 50 µA
Level Output Voltage
IIN Maximum Input
Leakage Current
*VIN=VIH or VIL
IOL=12 mA
IOL=24 mA
IOL=24 mA
VIN=VCC or GND
3.0 2.9
4.5 4.4
5.5 5.4
3.0 2.56
4.5 3.86
5.5 4.86
3.0 0.1
4.5 0.1
5.5 0.1
3.0 0.36
4.5 0.36
5.5 0.36
5.5 ±0.1
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
IOLD +Minimum Dynamic VOLD=1.65 V Max
Output Current
5.5
75
IOHD +Minimum Dynamic VOHD=3.85 V Min
Output Current
5.5
-75
ICC Maximum Quiescent VIN=VCC or GND
Supply Current
(per Package)
5.5 4.0
40
* All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC
Unit
V
V
V
V
µA
mA
mA
µA
3


3Pages


IN74AC109 電子部品, 半導体
IN74AC109
N SUFFIX PLASTIC DIP
(MS - 001BB)
A
16 9
B
18
FL
C
-T- SEATING
PLANE
N
G
KM
D
H
NOTES:
0.25 (0.010) M T
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
J
Symbol
A
B
C
D
F
G
H
J
K
L
M
N
Dimension, mm
MIN MAX
18.67 19.69
6.1 7.11
5.33
0.36 0.56
1.14 1.78
2.54
7.62
0° 10°
2.92 3.81
7.62 8.26
0.2 0.36
0.38
D SUFFIX SOIC
(MS - 012AC)
A
16 9
H BP
1G
8
C
R x 45
-T-
D
SEATING
K PLANE
0.25 (0.010) M T C M
J
F
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B 0.25 mm (0.010) per side.
Symbol
A
B
C
D
F
G
MH
J
K
M
P
R
Dimension, mm
MIN MAX
9.8 10
3.8 4
1.35 1.75
0.33 0.51
0.4 1.27
1.27
5.72
0° 8°
0.1 0.25
0.19 0.25
5.8 6.2
0.25 0.5
6

6 Page



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共有リンク

Link :


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IK Semiconductor
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IN74AC109

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

ETC
ETC
IN74AC109

Dual J-K Positive-Edge-Triggered Flip-Flop

IK Semiconductor
IK Semiconductor


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