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PDF IN74AC192 Data sheet ( Hoja de datos )
| Número de pieza | IN74AC192 | |
| Descripción | Synchronous Decade Up/Down Counter | |
| Fabricantes | IK Semiconductor | |
| Logotipo |  |
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TECHNICAL DATA
IN74AC192
Presettable BCD/Decade UP/DOWN Counter
High-Speed Silicon-Gate CMOS
The IN74AC192 is identical in pinout to the LS/ALS192,
HC/HCT192. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS outputs.
The counter has two separate clock inputs, a Count Up Clock and
Count Down Clock inputs. The direction of counting is determined by
which input is clocked. The outputs change state synchronous with the
LOW-to-HIGH transitions on the clock inputs. This counter may be
preset by entering the desired data on the P0, P1, P2, P3 input. When the
Parallel Load input is taken low the data is loaded independently of either
clock input. This feature allows the counters to be used as devide-by-n by
modifying the count lenght with the preset inputs. In addition the counter
can also be cleared. This is accomplished by inputting a high on the
Master Reset input. All 4 internal stages are set to low independently of
either clock input.Both a Terminal Count Down (TCD) and Terminal
Count Up (TCU) Outputs are provided to enable cascading of both up and
down counting functions. The TCD output produces a negative going
pulse when the counter underflows and TCU outputs a pulse when the
counter overflows. The counter can be cascaded by connecting the TCU
and TCD outputs of one device to the Count Up Clock and Count Down
Clock inputs, respectively, of the next device.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA, 0.1 µA @ 25°C
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74AC192N Plastic
IN74AC192D SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheet4u.com
PIN 16 =VCC
PIN 8 = GND
1
1 page  
IN74AC192
TIMING REQUIREMENTS (CL=50pF, Input tr=tf=3.0 ns)
Symbol
Parameter
VCC*
V
tsu Minimum Setup Time, Pn to PL (Figure 7)
th Minimum Hold Time, PL to Pn (Figure 7)
tw Minimum Pulse Width, PL (Figure 4)
tw Minimum Pulse Width, CPU or CPD
(Figure 1)
tw Minimum Pulse Width, MR (Figure 5)
trec Minimum Recovery Time, PL to CPU or CPD
(Figure 5)
trec Minimum Recovery Time, MR to CPU or CPD
(Figure 5)
*Voltage Range 3.3 V is 3.3 V ±0.3 V
Voltage Range 5.0 V is 5.0 V ±0.5 V
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Guaranteed Limits
25 °C
-40°C to
85°C
9 10
67
-1.0 0
-1.0 0
17 21
12 13
11 12
89
14 16
10 12
9 10
12 13
17 21
12 14
Unit
ns
ns
ns
ns
ns
ns
ns
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet IN74AC192.PDF ] | |
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