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IN74HC651A の電気的特性と機能

IN74HC651AのメーカーはIK Semiconductorです、この部品の機能は「Octal Bus Transceiver/Register」です。


製品の詳細 ( Datasheet PDF )

部品番号 IN74HC651A
部品説明 Octal Bus Transceiver/Register
メーカ IK Semiconductor
ロゴ IK Semiconductor ロゴ 




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IN74HC651A Datasheet, IN74HC651A PDF,ピン配置, 機能
TECHNICAL DATA
IN74HC651A
Octal 3-State Bus Transceivers
and D Flip-Flops
High-Performance Silicon-Gate CMOS
The IN74HC651A is identical in pinout to the LS/ALS651. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
These devices consist of bus transceiver circuits, D-type flip-flop, and
control circuitry arranged for multiplex transmission of data directly from
the data bus or from the internal storage registers. Direction and Output
Enable are provided to select the read-time or stored data function. Data
on the A or B Data bus, or both, can be stored in the internal D flip-flops
by low-to-high transitions at the appropriate clock pins (A-to-B Clock or
B-to-A Clock) regardless of the select or enable or enable control pins.
When A-to-B Source and B-to-A Source are in the real-time transfer
mode, it is also possible to store data without using the internal D-type
flip-flops by simulta-neously enabling Direction and Output Enable. In
this configuration each output reinforces its input. Thus, when all other
data sources to the two sets of bus lines are at high impedance, each set of
bus lines will remain at its last state.
The IN74HC651A has inverted outputs.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC651AN Plastic
IN74HC651ADW SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheet4u.coPmPININ1224==GVNCCD
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IN74HC651A pdf, ピン配列
IN74HC651A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VIH Minimum High-
VOUT=0.1 V or VCC-0.1 V
Level Input Voltage IOUT⎢≤ 20 µA
VIL Maximum Low -
VOUT=0.1 V or VCC-0.1 V
Level Input Voltage IOUT⎢ ≤ 20 µA
VOH Minimum High-
VIN=VIH or VIL
Level Output Voltage IOUT⎢ ≤ 20 µA
VIN=VIH or VIL
IOUT⎢ ≤ 6.0 mA
IOUT⎢ ≤ 7.8 mA
VOL Maximum Low-
VIN= VIL or VIH
Level Output Voltage IOUT⎢ ≤ 20 µA
IIN Maximum Input
Leakage Current
VIN=VIH or VIL
IOUT⎢ ≤ 6.0 mA
IOUT⎢ ≤ 7.8 mA)
VIN=VCC or GND
(Pins 1,2,3,21,22,and 23)
IOZ Maximum Three-
State Leakage
Current
Output in High-Impedance
State
VIN= VIL or VIH
VOUT=VCC or GND,
I/O Pins
ICC Maximum Quiescent VIN=VCC or GND
Supply Current
IOUT=0µA
(per Package)
VCC Guaranteed Limit
V 25 °C 85 125
to °C °C
-55°C
2.0 1.5 1.5 1.5
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
2.0 0.5 0.5 0.5
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
2.0 1.9 1.9 1.9
4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Unit
V
V
V
4.5 3.98 3.84 3.7
6.0 5.48 5.34 5.2
2.0 0.1 0.1 0.1
4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
V
4.5 0.26 0.33 0.4
6.0 0.26 0.33 0.4
6.0 ±0.1 ±1.0 ±1.0 µA
6.0 ±0.5 ±5.0 ±10 µA
6.0 8.0 80 160 µA
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IN74HC651A 電子部品, 半導体
IN74HC651A
FUNCTION TABLE
Dir. OE CAB CBA SAB SBA
A
B
FUNCTION
INPUTS INPUTS Both the A bus and the B bus are inputs.
L HXXXX
Z
Z The output functions of the A and B bus
are disabled.
X X INPUTS INPUTS Both the A and B bus are used for inputs
to the internal flip-flops. Data at the bus
will be stored on low to high transition of
the clock inputs.
OUTPUTS INPUTS The A bus are outputs and the B bus are
inputs.
X* X X L
H
L
L The data at the B bus are displayed at the
H A bus.
L L X*
XL
H
L
L The data at the B bus are displayed at the
H A bus. The data of the B bus are stored to
the internal flip-flops on low to high
transition of the clock pulse.
X* X X H
Qn
X The data stored to the internal flip-flops,
are displayed at the A bus.
X*
XH
L
H The data at the B bus are stored to the
H L internal flip-flops on low to high
transition of the clock pulse. The states of
the internal flip-flops output directly to
the A bus.
INPUTS OUTPUTS The A bus are inputs and the B bus are
outputs.
X X* L X
H
L
L The data at the A bus are displayed at the
H B bus.
HH
X* L X
H
L
L The data at the B bus are displayed at the
H A bus. The data of the B bus are stored to
the internal flip-flops on low to high
transition of the clock pulse.
X X* H X
X
Qn The data stored to the internal flip-flops
are displayed at the B bus.
X* H X
H
L
L The data at the A bus are stored to the
H internal flip-flops on low to high
transition of the clock pulse. The states of
the internal flip-flops output directly to
the B bus.
OUTPUTS OUTPUTS Both the A bus and the B bus are outputs
H LXXHH
Qn
Qn The data stored to the internal flip-flops
are displayed at the A and B bus
respectively.
HH
Qn
Qn The output at the A bus are displayed at
the B bus, the output at the B bus are
displayed at the A bus respec.
X : DON’T CARE
Z : HIGH IMPEDANCE
Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION
OF THE CLOCK INPUTS
* : THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW
TO TRANSITION OF THE CLOCK INPUTS
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部品番号部品説明メーカ
IN74HC651A

Octal Bus Transceiver/Register

IK Semiconductor
IK Semiconductor


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