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IW4042B の電気的特性と機能

IW4042BのメーカーはIK Semiconductorです、この部品の機能は「Quad Clocked D-Latch」です。


製品の詳細 ( Datasheet PDF )

部品番号 IW4042B
部品説明 Quad Clocked D-Latch
メーカ IK Semiconductor
ロゴ IK Semiconductor ロゴ 




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IW4042B Datasheet, IW4042B PDF,ピン配置, 機能
TECHNICAL DATA
Quad Clocked «D» Latch
High-Voltage Silicon-Gate CMOS
IW4042B
IW4042B types contain four latch circuits, each strobed by a common
clock. Complementary buffered outputs are available from each circuit.
The impedance of the n- and p-channel output devices is balanced and all
outputs are electrically identical. Information present at the data input is
transferred to outputs Q and Q during the CLOCK level which is
programmed by the POLARITY input. For POLARITY = 0 the transfer
occurs during the 0 CLOCK level and for POLARITY = 1 the transfer
occurs during the 1 CLOCK level. The outputs follow the data input
providing the CLOCK and POLARITY levels defined above are present.
When a CLOCK transition occurs (positive for POLARITY = 0 and
negative for POLARTY = 1) the information present at the input during
the CLOCK transition is retained at the outputs until an opposite CLOCK
transition occurs.
The IW4042B types are supplied in 16-lead hermetic dual-in-line
ceramic packages (D and F suffixes); 16-lead dual-in-line plastic package
(E suffix), and in chip form (H suffix).
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4042BN Plastic
IW4042BD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheet4uPPIIN.Nc81o6==GmVNCDC
FUNCTION TABLE
Inputs
Clock
Polarity
00
10
11
01
Outputs
Q
D
Latch
D
Latch
1

1 Page





IW4042B pdf, ピン配列
IW4042B
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VIH Minimum High-Level VOUT=0.5 V or VCC - 0.5 V
Input Voltage
VOUT=1.0 V or VCC - 1.0 V
VOUT=1.5 V or VCC - 1.5 V
VIL Maximum Low -
VOUT=0.5 V or VCC - 0.5 V
Level Input Voltage VOUT=1.0 V or VCC - 1.0 V
VOUT=1.5 V or VCC - 1.5 V
VOH Minimum High-Level VIN=GND or VCC
Output Voltage
VOL Maximum Low-Level VIN=GND or VCC
Output Voltage
IIN Maximum Input
Leakage Current
VIN= GND or VCC
IСС Maximum Quiescent VIN= GND or VCC
Supply Current
(per Package)
IOL Minimum Output
VIN= GND or VCC
Low (Sink) Current VOL=0.4 V
VOL=0.5 V
VOL=1.5 V
IOH Minimum Output
VIN= GND or VCC
High (Source) Current VOH=2.5 V
VOH=4.6 V
VOH=9.5 V
VOH=13.5 V
VСС Guaranteed Limit
V -55°C 25°C 125 Unit
°C
5.0 3.5
10 7
15 11
3.5 3.5 V
77
11 11
5.0 1.5
10 3
15 4
1.5 1.5 V
33
44
5.0 4.95 4.95 4.95 V
10 9.95 9.95 9.95
15 14.95 14.95 14.95
5.0 0.05
10 0.05
15 0.05
0.05 0.05 V
0.05 0.05
0.05 0.05
18 ±0.1 ±0.1 ±1.0 µA
5.0 1
10 2
15 4
20 20
1 30 µA
2 60
4 120
20 600
5.0 0.64
10 1.6
15 4.2
mA
0.51 0.36
1.3 0.9
3.4 2.4
mA
5.0 -2.0
-1.6 -1.15
5.0 -0.64 -0.51 -0.36
10 -1.6
-1.3 -0.9
15 -4.2
-3.4 -2.4
3


3Pages


IW4042B 電子部品, 半導体
IW4042B
N SUFFIX PLASTIC
(MS - 001BB)
A
16 9
B
18
FL
C
-T- SEATING
PLANE
N
G KM
D
0.25 (0.010) M T
J
H
NOTES:
1. imensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
Symbol
A
B
C
D
F
G
H
J
K
L
M
N
Dimensions, mm
MIN
18.67
MAX
19.69
6.10 7.11
5.33
0.36 0.56
1.14 1.78
2.54
7.62
0° 10°
2.92 3.81
7.62 8.26
0.20 0.36
0.38
D SUFFIX SOIC
(MS - 012AC)
A
16 9
H BP
1G
8
C
-T-
D
SEATING
K PLANE
J
0.25 (0.010) M T C M
R x 45
F
M
NOTES:
1.Dimensions A and B do not include mold flash or protrusion.
2.Maximum mold flash or protrusion 0.15 mm (0.006) per side for A, for
B - 0.25 mm (0.010) per side.
Symbol.
A
B
C
D
F
G
H
J
K
M
P
R
Dimensions, mm
MIN
9.80
MAX
10.0
3.80 4.00
1.35 1.75
0.33 0.51
0.40 1.27
1.27
5.72
0° 8°
0.10 0.25
0.19 0.25
5.80 6.20
0.25 0.50
6

6 Page



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共有リンク

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部品番号部品説明メーカ
IW4042B

Quad Clocked D-Latch

IK Semiconductor
IK Semiconductor


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