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27C240 の電気的特性と機能

27C240のメーカーはETCです、この部品の機能は「NM27C240」です。


製品の詳細 ( Datasheet PDF )

部品番号 27C240
部品説明 NM27C240
メーカ ETC
ロゴ ETC ロゴ 




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27C240 Datasheet, 27C240 PDF,ピン配置, 機能
www.DataSheet4U.com
July 1998
NM27C240
4,194,304-Bit (256k x 16) High Performance
CMOS EPROM
General Description
The NM27C240 is a high performance Electrically Programmable
UV erasable ROM (EPROM). It contains 4,194,304 bits config-
ured as 256k x 16 bits. It is offered in both erasable versions for
prototyping and early production applications as well as non-
erasable, plastic packaged versions that are ideal for high volume
and automated assembly applications.
The NM27C240 operates from a single 5V ±10% supply in the
read mode.
The NM27C240 is offered in both DIP and surface mount pack-
ages. The DIP package is a 40-pin dual-in-line ceramic with a
quartz window to allow erasing. The surface mount package is a
44-pin PLCC that is offered in OTP.
This EPROM is manufactured using Fairchild’s proprietary AMG™
EPROM technology for an excellent combination of speed and
economy while providing excellent reliability.
Features
s High performance CMOS
— 100 ns access time
s Fast turn-off for microprocessor compatibility
s Simplified upgrade path
— VPP and PGM are “Don’t Care” during normal read
operation
s Compatible with 27240 and 27C240 EPROMs
s JEDEC standard pin configuration
— 40-pin DIP package
— 44-pin PLCC package
s Manufacturer’s identification code
s Fast programming algorithm
Block Diagram
Vcc
GND
Vpp
OE
CE/PGM
Output Enable
Chip Enable, and
Program Logic
Data Outputs O0 - O15
Output
Buffers
A0 - A17
Address
Inputs
Y
Decoder
X
Decoder
4,194,304-Bit
Cell Matrix
DS011949-1
AMG™ is a trademark of WSI, Inc.
© 1998 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com

1 Page





27C240 pdf, ピン配列
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Absolute Maximum Ratings (Note 1)
Storage Temperature
-65°C to +150°C
All Input Voltages except A9 with
Respect to Ground (Note 10)
-0.6V to +7V
VPP and A9 with
Respect to Ground
-0.6V to +14V
VCC Supply Voltage with
Respect to Ground
-0.6V to +7V
ESD Protection
>2000V
All Output Voltages with Respect
to Ground (Note 10)
VCC + 1.0V to GND - 0.6V
Operating Range
Range
Commercial
Industrial
Temperature
0°C to +70°C
-40V°C to +85°C
DC Read Characteristics Over Operating Range with VPP = VCC
Symbol
Parameter
Conditions
VIL Input Low Level
VIH Input High Level
VOL Output Low Voltage
IOL = 2.1 mA
VOH Output High Voltage
IOH = -2.5 mA
ISB1
VCC Standby Current (CMOS)
CE = VCC ±0.3V
ISB2 VCC Standby Current (TTL) CE = VIH
ICC VCC Active Current
CE = OE = VIL, I/O = 0 mA
f=5 MHz
IPP VPP Supply Current
VPP = VCC
ILI Input Load Current
VIN = 5.5V or GND
ILO Output Leakage Current
VOUT = 5.5V or GND
Min
-0.5
2.0
3.5
-1
-10
VCC Tolerance
+5V ±10%
+5V ±10%
Max
0.8
VCC +1
0.4
100
1
40
10
1
10
Units
V
V
V
V
µA
mA
mA
µA
µA
µA
AC Read Characteristics Over Operating Range with VPP = VCC
Symbol
Parameter
100 120
Min Max Min Max
tACC
tCE
tOE
tDF (Note 2)
tOH (Note 2)
Address to Output Delay
CE to Output Delay
OE to Output Delay
Output Disable to Output Float
Output Hold from Addresses CE or
OE , Whichever Occurred First
100 120
100 120
50 50
35 35
00
150
Min Max
150
150
50
45
0
Units
ns
Capacitance TA = +25˚C, f = 1 MHz (Note 2)
Symbol
Parameter
Conditions
CIN
COUT
Input Capacitance
Output Capacitance
VIN = 0V
VOUT = 0V
Typ
12
13
Max
20
20
Units
pF
pF
3 www.fairchildsemi.com


3Pages


27C240 電子部品, 半導体
www.DataSheet4U.com
Turbo Programming Algorithm Flow Chart
VCC = 6.5V VPP = 12.75V
n=0
ADDRESS = FIRST LOCATION
PROGRAM ONE 50µs PULSE
INCREMENT n
DEVICE
FAILED
NO
YES n = 10?
FAIL VERIFY
BYTE
PASS
LAST NO
ADDRESS
?
YES
INCREMENT
ADDRESS
n=0
ADDRESS = FIRST LOCATION
INCREMENT
ADDRESS
VERIFY FAIL
BYTE
PASS
NO LAST
ADDRESS
?
YES
PROGRAM ONE
50 µs
PULSE
CHECK ALL BYTES
1ST: VCC = VPP = 6.0V
2ND: VCC = VPP = 4.2V
Note: The standard National Semiconductor algorithm may also be used but it will have longer programming time.
FIGURE 1.
DS011949-6
6 www.fairchildsemi.com

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共有リンク

Link :


部品番号部品説明メーカ
27C240

NM27C240

ETC
ETC
27C240

4M CHMOS EPROM

Intel
Intel


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