DataSheet.jp

ISL6548 の電気的特性と機能

ISL6548のメーカーはIntersil Corporationです、この部品の機能は「ACPI Regulator/Controller for Dual Channel DDR Memory Systems」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6548
部品説明 ACPI Regulator/Controller for Dual Channel DDR Memory Systems
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




このページの下部にプレビューとISL6548ダウンロード(pdfファイル)リンクがあります。

Total 15 pages

No Preview Available !

ISL6548 Datasheet, ISL6548 PDF,ピン配置, 機能
®
Data Sheet
February 9, 2005
ISL6548
FN9188.1
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6548 provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply VDDQ during S0/S1 and S3 states. During S0/S1
state, a fully integrated sink-source regulator generates an
accurate (VDDQ/2) high current VTT voltage without the
need for a negative supply. Two LDO controllers are also
integrated for the GMCH core voltage regulation and for the
GMCH/CPU VTT termination voltage regulation.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH/CPU VTT termination voltage is
within spec and operational.
Each output is monitored for undervoltage events. The
switching regulator also has overvoltage and overcurrent
protection. Thermal shutdown is integrated.
Pinout
ISL6548 (6x6 QFN)
TOP VIEW
28 27 26 25 24 23 22
5VSBY 1
21 DRIVE4
S3# 2
20 REFADJ4
P12V 3
GND 4
DDR_VTT 5
GND
29
19 DRIVE3
18 FB3
17 FB4
DDR_VTT 6
16 COMP
VDDQ 7
15 FB
8 9 10 11 12 13 14
Features
• Generates 4 Regulated Voltages
- Synchronous Buck PWM Controller for DDR VDDQ
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference for DDR VTT
- LDO Regulator for GMCH Core
- Sink/Source LDO Regulator for CPU/GMCH VTT
Termination
• ACPI compliant sleep state control
• Glitch-free Transitions During State Changes
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- All Outputs: ±2% Over Temperature
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Overvoltage Monitoring on All Outputs
• OCP on the Switching Regulator
• Integrated Thermal Shutdown Protection
• Pb-Free Available (RoHS Compliant)
Applications
Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
Graphics cards - GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
Ordering Information
TEMP.
PART NUMBER RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6548CRZ
(Note)
0 to 70 28 Ld 6x6 QFN (Pb-free) L28.6x6
ISL6548CRZ-T
(Note)
0 to 70 28 Ld 6x6 QFN
L28.6x6
Tape and Reel (Pb-free)
ISL6548CRZ A
(Note)
0 to 70 28 Ld 6x6 QFN (Pb-free) L28.6x6
ISL6548CRZA-T
(Note)
0 to 70 28 Ld 6x6 QFN
L28.6x6
Tape and Reel (Pb-free)
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which are
RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL6548 pdf, ピン配列
ISL6548
Simplified Power System Diagram
5VSBY
12V
VDDQ
SLP_S3
SLP_S5
Q3
VGMCH
Q4
+
SLEEP
STATE
LOGIC
TWO STAGE
LINEAR
CONTROLLER
PWM
CONTROLLER
ISL6548
VTT_GMCH/CPU
+
Q5
Q6
LINEAR
CONTROLLER
VTT
REGULATOR
5VDUAL
Q1
VDDQ
+
Q2
VREF
VTT
+
Typical Application
5VSBY 12V
5VDUAL
VDDQ_DDR
Q3
SLP_S5
SLP_S3
VGMCH
Q4
R5
R6
Q5
VTT_GMCH/CPU
R7
R8
Q6
VIDPGD
S5#
S3#
DRIVE4
FB4
REFADJ4
DRIVE3
FB3
BOOT
ISL6548
OCSET
UGATE
PHASE
LGATE
DDR_VDDQ(x2)
COMP
DRIVE2_U
FB
DBOOT
ROCSET
CBOOT
C1
R2 C2
R4
Q1
Q2
R3 C3
R1
VDDQ_DDR
+
FB2
DRIVE2_L
GND
VREF_IN
DDR_VTT(x2)
DDR_VTTSNS
VTT_DDR
3 FN9188.1
February 9, 2005


3Pages


ISL6548 電子部品, 半導体
ISL6548
Functional Pin Description
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6548. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6548 enters a reduced
power mode and draws less than 1mA (ICC_S5) from the
5VSBY supply. The supply to 5VSBY should be locally
bypassed using a 0.1µF capacitor.
P12V (Pin 3)
The VTT regulation circuit and the Linear Drivers are
powered by P12V. P12V is not required during S3/S4/S5
operation. P12V is typically connected to the +12V rail of an
ATX power supply.
GND (Pins 4, 27, 29)
The GND terminals of the ISL6548 provide the return path
for the VTT LDO, and switching MOSFET gate drivers. High
ground currents are conducted directly through the exposed
paddle of the QFN package which must be electrically
connected to the ground plane through a path as low in
inductance as possible.
UGATE (Pin 26)
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
LGATE (Pin 28)
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the lower
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the lower MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
FB (Pin 15) and COMP (Pin 16)
The VDDQ switching regulator employs a single voltage
control loop. FB is the negative input to the voltage loop error
amplifier. The VDDQ output voltage is set by an external
resistor divider connected to FB. With a properly selected
divider, VDDQ can be set to any voltage between the power
rail (reduced by converter losses) and the 0.8V reference.
Loop compensation is achieved by connecting an AC
network across COMP and FB.
The FB pin is also monitored for under and overvoltage
events.
PHASE (Pin 24)
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
OCSET (Pin 22)
Connect a resistor (ROCSET) from this pin to the drain of the
upper MOSFET. ROCSET, an internal 20µA current source
(IOCSET), and the upper MOSFET on-resistance (rDS(ON))
set the converter overcurrent (OC) trip point according to the
following equation:
IPEAK = I--O-----C----S---r-E-D---T-S---x-(--RO-----ON----)C----S----E----T--
An overcurrent trip cycles the soft-start function.
VDDQ (Pins 7, 8)
The VDDQ pins should be connected externally together to
the regulated VDDQ output. During S0/S1 states, the VDDQ
pins serve as inputs to the VTT regulator and to the VTT
Reference precision divider.
DDR_VTT (Pins 5, 6)
The DDR_VTT pins should be connect externally together.
During S0/S1 states, the DDR_VTT pins serve as the
outputs of the VTT linear regulator. During S3 state, the VTT
regulator is disabled.
DDR_VTTSNS (Pin 9)
VTTSNS is used as the feedback for control of the VTT linear
regulator. Connect this pin to the VTT output at the physical
point of desired regulation.
VREF_IN (Pin 14)
A capacitor, CSS, connected between VREF_IN and ground
is required. This capacitor and the parallel combination of
the Upper and Lower Divider Impedance (RU||RL), sets the
time constant for the start up ramp when transitioning from
S3/S4/S5 to S0/S1/S2.
The minimum value for CSS can be found through the
following equation:
CSS > C---1--V-0---T----T-2--O--A---U----T-R-----U--V---|-D|---R-D---L-Q---
The calculated capacitance, CSS, will charge the output
capacitor bank on the VTT rail in a controlled manner without
reaching the current limit of the VTT LDO.
BOOT (Pin 25)
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
6 FN9188.1
February 9, 2005

6 Page



ページ 合計 : 15 ページ
 
PDF
ダウンロード
[ ISL6548 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
ISL6540

Single-Phase Buck PWM Controller

Intersil Corporation
Intersil Corporation
ISL6540A

Single-Phase Buck PWM Controller

Intersil Corporation
Intersil Corporation
ISL65426

6A Dual Synchronous Buck Regulator

Intersil Corporation
Intersil Corporation
ISL6545

5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

Intersil Corporation
Intersil Corporation


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap