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PDF ISL6548A Data sheet ( Hoja de datos )
| Número de pieza | ISL6548A | |
| Descripción | ACPI Regulator/Controller for Dual Channel DDR Memory Systems | |
| Fabricantes | Intersil Corporation | |
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®
PRELIMINARY
Data Sheet
July 22, 2005
ISL6548A
FN9189.1
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6548A provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply VDDQ during S0/S1 and S3 states. During S0/S1
state, a fully integrated sink-source regulator generates an
accurate (VDDQ/2) high current VTT voltage without the
need for a negative supply. A second PWM controller, which
requires external MOSFET drivers, is available for regulation
of the GMCH Core voltage. A sink/source LDO controller is
also integrated for the CPU/GMCH VTT termination voltage
regulation. Another LDO is available for the ICH7 voltage.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH and CPU VTT termination voltage
is within spec and operational.
All outputs, except VICH7, have undervoltage protection. The
switching regulator also has overvoltage and overcurrent
protection. Thermal shutdown is integrated.
Features
• Generates 5 Regulated Voltages
- Synchronous Buck PWM Controller for DDR VDDQ
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference for DDR VTT
- PWM Regulator for GMCH Core
- Sink/Source LDO Regulator for CPU/GMCH VTT
Termination
- LDO Regulator for ICH7
• ACPI compliant sleep state control
• Glitch-free Transitions During State Changes
• VDDQ PWM Controller Drives Low Cost N-Channel
MOSFETs
• 250kHz Constant Frequency Operation
- Both PWM controllers are Phase Shifted 180°
• Tight Output Voltage Regulation
- All Outputs: ±2% Over Temperature
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Overvoltage Monitoring
• OCP on the VDDQ Switching Regulator
• Integrated Thermal Shutdown Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
• Graphics cards - GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6548A
Absolute Maximum Ratings
5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V
Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . +6.0V
All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
QFN Package . . . . . . . . . . . . . . . . . . .
32
4
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
5VSBY SUPPLY CURRENT
Nominal Supply Current
POWER-ON RESET
ICC_S0
ICC_S5
S3# & S5# HIGH, UGATE/LGATE Open
5.5 7.0 8.0
S5# LOW, S3# Don’t Care, UGATE/LGATE Open -
700 850
mA
µA
Rising 5VSBY POR Threshold
4.10 - 4.45
V
Falling 5VSBY POR Threshold
3.60 - 3.95
V
Rising P12V POR Threshold
10.0 - 10.5
V
Falling P12V POR Threshold
8.80 - 9.75
V
OSCILLATOR AND SOFT-START
PWM Frequency
Ramp Amplitude
Soft-Start Interval
REFERENCE VOLTAGE
fOSC
∆VOSC
tSS
220 250 280
- 1.5 -
6.5 8.2 9.5
kHz
V
ms
Reference Voltage
System Accuracy
VREF
- 0.800 -
-2.0 - +2.0
V
%
VDDQ AND VGMCH PWM CONTROLLER ERROR AMPLIFIERS
DC Gain
Guaranteed By Design
- 80 -
dB
Gain-Bandwidth Product
GBWP
15 -
- MHz
Slew Rate
SR
- 6 - V/µs
CONTROL I/O (S3#, S5#)
LOW Level Input Threshold
0.75 -
-
V
HIGH Level Input Threshold
- - 2.2 V
5 FN9189.1
July 22, 2005
5 Page 
ISL6548A
diagrams on page 4). An internal 20µA (typical) current sink
develops a voltage across ROCSET that is referenced to the
converter input voltage. When the voltage across the upper
MOSFET (also referenced to the converter input voltage)
exceeds the voltage across ROCSET, the overcurrent function
initiates a soft-start sequence. The initiation of soft-start may
affect other regulators. The VTT_DDR regulator is directly
affected as it receives its reference and input from VDDQ.
The overcurrent function will trip at a peak inductor current
(IPEAK) determined by:
IPEAK = I--O-----C----S----E-r--D-T---S--x--(--O-R----N-O---)-C-----S----E---T--
where IOCSET is the internal OCSET current source (20µA
typical). The OC trip point varies mainly due to the MOSFET
rDS(ON) variations. To avoid overcurrent tripping in the
normal operating load range, find the ROCSET resistor from
the equation above with:
1. The maximum rDS(ON) at the highest junction
temperature.
2. The minimum IOCSET from the specification table.
3. Determine IPEAK for IPEAK > IOUT(MAX) + (---∆-2---I---) ,
where ∆I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
A small ceramic capacitor should be placed in parallel with
ROCSET to smooth the voltage across ROCSET in the
presence of switching noise on the input voltage.
Thermal Protection (S0/S3 State)
If the ISL6548A IC junction temperature reaches a nominal
temperature of 140°C, all regulators will be disabled. The
ISL6548A will not re-enable the outputs until the junction
temperature drops below 110°C and either the bias voltage is
toggled in order to initiate a POR or the SLP_S5 signal is
forced LOW and then back to HIGH.
Shoot-Through Protection
A shoot-through condition occurs when both the upper and
lower MOSFETs are turned on simultaneously, effectively
shorting the input voltage to ground. To protect from a shoot-
through condition, the ISL6548A incorporates specialized
circuitry on the VDDQ regulator which insures that
complementary MOSFETs are not ON simultaneously.
The adaptive shoot-through protection utilized by the VDDQ
regulator looks at the lower gate drive pin, LGATE, and the
upper gate drive pin, UGATE, to determine whether a
MOSFET is ON or OFF. If the voltage from UGATE or from
LGATE to GND is less than 0.8V, then the respective
MOSFET is defined as being OFF and the other MOSFET is
allowed to turned ON. This method allows the VDDQ
regulator to both source and sink current.
Since the voltage of the MOSFET gates are being measured
to determine the state of the MOSFET, the designer is
encouraged to consider the repercussions of introducing
external components between the gate drivers and their
respective MOSFET gates before actually implementing
such measures. Doing so may interfere with the shoot-
through protection.
Application Guidelines
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
250kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit board design minimizes these
voltage spikes.
As an example, consider the turn-off transition of the control
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET. Any
parasitic inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide traces minimizes the magnitude of voltage
spikes.
There are two sets of critical components in the ISL6548A
switching converter. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are
the small signal components which connect to sensitive
nodes or supply critical bypass current and signal coupling.
A multi-layer printed circuit board is recommended. Figure 2
shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
In order to dissipate heat generated by the internal VTT
LDO, the ground pad, pin 29, should be connected to the
internal ground plane through at least four vias. This allows
11 FN9189.1
July 22, 2005
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ISL6548A.PDF ] | |
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