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ST95010 の電気的特性と機能

ST95010のメーカーはST Microelectronicsです、この部品の機能は「(ST950x0) 4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe」です。


製品の詳細 ( Datasheet PDF )

部品番号 ST95010
部品説明 (ST950x0) 4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe
メーカ ST Microelectronics
ロゴ ST Microelectronics ロゴ 




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ST95010 Datasheet, ST95010 PDF,ピン配置, 機能
ST95040
ST95020, ST95010
4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE
– 4.5V to 5.5V for ST950x0
– 2.5V to 5.5V for ST950x0W
SPI BUS COMPATIBLE SERIAL INTERFACE
2 MHz CLOCK RATE MAX
BLOCK WRITE PROTECTION
STATUS REGISTER
16 BYTE PAGE MODE
WRITE PROTECT
SELF-TIMED PROGRAMMING CYCLE
E.S.D.PROTECTION GREATER than 4000V
SUPPORTS POSITIVE CLOCK SPI MODES
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
The ST950x0 is a family of Electrically Erasable
Programmable Memories (EEPROM) fabricated
with STMicroelectronics’s High Endurance Single
Polysilicon CMOS technology. Each memory is
accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q).
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
HOLD
Hold
VCC Supply Voltage
VSS Ground
VCC
D
C
S
W
HOLD
ST950x0
Q
VSS
AI01435B
June 1998
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ST95010 pdf, ピン配列
Figure 3. Data and Clock Timing
CPOL CPHA
00
C
11
C
D or Q
MSB
Figure 4. Microcontroller and SPI Interface Set-up
MICROCONTROLLER
(ST6, ST7, ST9, ST10, OTHERS)
SPI Interface with
(CPOL, CPHA) =
(’0’, ’0’) or (’1’, ’1’)
SCK
SDI
SDO
ST95040, ST95020, ST95010
LSB
AI01438
C ST95xx0
Q
D
AI01439B
Serial Clock (C). The serial clock provides the
timing of the serial interface. Instructions, ad-
dresses, or data present at the input pin are latched
on the rising edge of the clock input, while data on
the Q pin changes after the falling edge of the clock
input.
Chip Select (S). When S is high, the Memory is
deselected and the Q output pin is at high imped-
ance and, unless an internal write operation is
underway the Memory will be in the standby power
mode. S low enables the Memory, placing it in the
active power mode. It should be noted that after
power-on, a high to low transition on S is required
prior to the start of any operation.
Write Protect (W). This pin is for hardware write
protection. When W is low, writes to the Memory
are disabled but any other operationsstay enabled.
When W is high, all writes operationsare available.
W going low at any time before the last bit D0 of
the data streamwill reset the write enable latch and
prevent programming. No action on W or on the
write enable latch can interrupt a write cycle which
has commenced.
3/18


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ST95010 電子部品, 半導体
ST95040, ST95020, ST95010
Figure 6. Read Operation Sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION
BYTE ADDRESS
D A8 A7 A6 A5 A4 A3 A2 A1 A0
HIGH IMPEDANCE
Q
DATA OUT
76543210
AI01440
Notes: A8 = A7 = 0 on ST95010; A8 = 0 on ST95020; A8 is only active on ST95040.
Table 4. Write Protected Block Size
Status Register Bits
BP1 BP0
Protected Block
0 0 none
0 1 Upper quarter
1 0 Upper half
1 1 Whole memory
Array Address Protected
ST95040
ST95020
ST95010
none
none
none
180h - 1FFh
C0h - FFh
60h - 7Fh
100h - 1FFh
80h - FFh
40h - 7Fh
000h - 1FFh
00h - FFh
00h - 7Fh
Write Status Register (WRSR)
The WRSR instruction allows the user to select the
size of protected memory. The user may read the
blocks but will be unable to write within the pro-
tected blocks. The blocks and respective WRSR
control bits are shown in Table 4.
When the WRSR instruction and the 8 bits of the
Status Register are latched-in, the internal write
cycle is then triggered by the rising edge of S.
This rising edge of S must appear no later than the
16th clock cycle of the WRSR instruction of the
Status Register content (it must not appear a 17th
clock pulse before the rising edge of S), otherwise
the internal write sequence is not performed.
Read Operation
The chip is firstselected by putting S low. The serial
one byte read instruction is followed by a one byte
address (A7-A0), each bit being latched-in during
the rising edge of the clock (C). Bit 3 (see Table 3)
of the read instruction contains address bit A8
(most significant address bit). Then the data stored
in the memory at the selected addressis shifted out
on the Q output pin; each bit being shifted out
during the falling edge of the clock (C). The data
stored in the memory at the next address can be
read in sequence by continuing to provide clock
pulses. The byte address is automatically incre-
mented to the next higher address after each byte
of data is shifted out. When the highest address is
reached, the address counter rolls over to 0h allow-
ing the read cycle to be continued indefinitely. The
read operation is terminated by deselecting the
chip. The chip can be deselectedat anytime during
data output. Any read attempt during a write cycle
will be rejected and will deselect the chip.
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部品番号部品説明メーカ
ST95010

(ST950x0) 4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe

ST Microelectronics
ST Microelectronics


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