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ST95022 の電気的特性と機能

ST95022のメーカーはST Microelectronicsです、この部品の機能は「2 Kbit Serial SPI EEPROM with High Speed Clock」です。


製品の詳細 ( Datasheet PDF )

部品番号 ST95022
部品説明 2 Kbit Serial SPI EEPROM with High Speed Clock
メーカ ST Microelectronics
ロゴ ST Microelectronics ロゴ 




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ST95022 Datasheet, ST95022 PDF,ピン配置, 機能
ST95022
2 Kbit Serial SPI EEPROM with High Speed Clock
HIGH SPEED CLOCK RATE:
– 2.1 MHz Max
1,000,000 ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE 4.5V to 5.5V SUPPLY VOLTAGE
SPI BUS COMPATIBLE SERIAL INTERFACE
BLOCK WRITE PROTECTION
STATUS REGISTER
16 BYTE PAGE MODE
WRITE PROTECT
SELF-TIMED PROGRAMMING CYCLE
E.S.D.PROTECTION GREATER than 4000V
SUPPORTS POSITIVE CLOCK SPI MODES
8
1
SO8 (M)
150mil Width
DESCRIPTION
The ST95022 is an high speed 2 Kbit Electrically
Erasable Programmable Memory (EEPROM) fab-
ricated with STMicroelectronics’s High Endurance
Single Polysilicon CMOS technology. The memory
is accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q).
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
HOLD
Hold
VCC Supply Voltage
VSS Ground
Figure 1. Logic Diagram
VCC
D
C
S
W
HOLD
ST95022
VSS
Q
AI01722
February 1999
1/16

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ST95022 pdf, ピン配列
Figure 3. Data and Clock Timing
CPOL CPHA
00
C
11
C
D or Q
MSB
Figure 4. Microcontroller and SPI Interface Set-up
MICROCONTROLLER
(ST6, ST7, ST9)
SPI Interface with
(CPOL, CPHA) =
('0', '0') or ('1', '1')
SCK
SDI
SDO
ST95022
LSB
AI01438
C ST95xx0
Q
D
AI01439
Hold (HOLD). The HOLD pin is used to pause
serial communications with a ST95022 without re-
setting the serial sequence. To take the Hold con-
dition into account, the product must be selected
(S = 0). Then the Hold state is validated by a high
to low transition on HOLD when C is low. To resume
the communications, HOLD is brought high while
C is low. During the Hold condition D, Q, and C are
at a high impedance state.
When the ST95022 is under the Hold condition, it
is possible to deselect the device. However, the
serial communications will remain paused after a
reselect, and the chip will be reset.
The ST95022 can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes: (CPOL, CPHA) = (’0’, ’0’) or
(CPOL, CPHA) = (’1’, ’1’).
For these two modes, input data is latched in by the
low to high transition of clock C, and output data is
available from the high to low transition of Clock
(C).
The difference between (CPOL, CPHA) = (0, 0) and
(CPOL, CPHA) = (1, 1) is the stand-by polarity: C
remains at ’0’ for (CPOL, CPHA) = (0, 0) and C
remains at ’1’ for (CPOL, CPHA) = (1, 1) when there
is no data transfer.
3/16


3Pages


ST95022 電子部品, 半導体
ST95022
Figure 6. Read Operation Sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION
BYTE ADDRESS
D A7 A6 A5 A4 A3 A2 A1 A0
HIGH IMPEDANCE
Q
DATA OUT
76543210
AI01558
Read Operation
The chip is first selected by putting S low. The serial
one byte read instruction is followed by a one byte
address (A7-A0), each bit being latched-in during
the rising edge of the clock (C). Then the data
stored in the memory at the selected address is
shifted out on the Q output pin; each bit being
shifted out during the falling edge of the clock (C).
The data stored in the memory at the next address
can be read in sequence by continuing to provide
clock pulses. The byte address is automatically
incremented to the next higher address after each
byte of data is shifted out. When the highest ad-
dress is reached, the address counter rolls over to
0h allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by dese-
lecting the chip. The chip can be deselected at any
time during data output. Any read attempt during a
write cycle will be rejected and will deselect the
chip.
Byte Write Operation
Prior to any write attempt, the write enable latch
must be set by issuing the WREN instruction. First
the device is selected (S = low) and a serial WREN
instruction byte is issued. Then the product is de-
selected by taking S high. After the WREN instruc-
tion byte is sent, the ST95022 will set the write
enable latch and then remain in standby until it is
deselected. Then the write state is entered by
selecting the chip, issuing two bytes of instruction
and address, and one byte of data.
Chip Select (S) must remain low for the entire
duration of the operation. The product must be
deselected just after the eighth bit of data has been
latched in. If not, the write process is cancelled. As
soon as the product is deselected, the self-timed
write cycle is initiated. While the write is in progress,
the status register may be read to check BP1, BP0,
WEL and WIP. WIP is high during the self-timed
write cycle. When the cycle is completed, the write
enable latch is reset.
6/16

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
ST95020

(ST950x0) 4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe

ST Microelectronics
ST Microelectronics
ST95022

2 Kbit Serial SPI EEPROM with High Speed Clock

ST Microelectronics
ST Microelectronics


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