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MV20556 の電気的特性と機能

MV20556のメーカーはMosel Vitelicです、この部品の機能は「8 - Bit MCU Mouse Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 MV20556
部品説明 8 - Bit MCU Mouse Controller
メーカ Mosel Vitelic
ロゴ Mosel Vitelic ロゴ 




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MV20556 Datasheet, MV20556 PDF,ピン配置, 機能
MOSEL VITELIC INC.
July 1997
Preliminary
Features
General 8051 instruction family compatible
Operate at voltage 5.0V.
No External Memory is supported
8 bit bus I/O ports
4 K byte ROM
128 byte RAM
128 byte depth stack
Two 16 bit Timers (Event Counters)
15 programmable I/O pins
Five interrupt sources
Programmable serial UART channel
Direct LED drive output
MV20556
8 - Bit MCU Mouse Controller
Bit operation instructions
Page free jumps
8 - bit Unsigned Division
8 - bit Unsigned Multiply
BCD arithmatic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A full duplex serial I/O port
Working at 16/25/40 MHz Clock
Full static operation: 3 MHz through 16 MHz
Description
The MVI MV20556 is an 8 - bit single chip
microcontroller. It provides hardware features and
powerful instruction set that are necessary to make it a
versatile and cost effective controller for mouse
applications which needs up to 4K byte internal
memory either for program or for data and mixed.
A serial input / output port is provided for I/O
expansion, Inter - processor communications, full
duplex UART.
Ordering Information
MV20556ajk - pqrs
a: process identifier. { C:=COMS }
jk: working clock in MHz. { 16 }
pqr: production code { 001, ..., 999 }
s: package type. { P: 20L 300 mil PDIP }
Postfix
blank
N
S
Package
dice
20L PDIP
20L SOP
Pin/Pad
Configuration
page 25
page 1
page 1
Dimension
page 25
page 23
page 24
Logo Size at
Top Marking
-
4.5 x 3.8 mm
4.0 x 3.4 mm
Pin Configuration
RES 1
RXD/P 3.0 2
TXD/P 3.1 3
XTA2 4
XTAL1 5
#INT0/P 3.2 6
#INT1/P 3.3 7
T0/P 3.4 8
T1/P 3.5 9
VSS 10
MV20556
20L PDIP
300 mil
(Top View)
20L SOP
(Top View)
20 VDD
19 P 1.7
18 P 1.6
17 P 1.5
16 P 1.4
15 P 1.3
14 P 1.2
13 P 1.1
12 P 1.0
11 P 3.7
Specifications subject to change without notice, contact your sales representatives for the most recent information.
1/27
PID256** 07/97

1 Page





MV20556 pdf, ピン配列
MOSEL VITELIC INC.
Preliminary
MV20556
Pin Descriptions
20L
PDIP
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
20L
SOP
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
dice Symbol
Active I/O Names
Pad#
4
5
6
7
8
9
10
11
12
13-15
17
18
19
20
21
22
23
24
1
2, 3
RES
RXD/P3.0
TXD/P3.1
XTAL2
XTAL1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
VSS
P3.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
VDD
i Reset
i/o bit 0 of Port 3 & Receive data
i/o bit 1 of Port 3 & Transmit data
i Crystal out
o Crystal in
L/- i/o bit 2 of Port 3 & low true Interrupt 0
L/- i/o bit 3 of Port 3 & low true Interrupt 1
i/o bit 4 of Port 3 & external input to Timer 0
i/o bit 5 of Port 3 & external input to Timer 1
i/o Sink Voltage, Ground
i/o bit 7 of Port 3
i/o bit 0 of Port 1
i/o bit 1 of Port 1
i/o bit 2 of Port 1
i/o bit 3 of Port 1
i/o bit 4 of Port 1
i/o bit 5 of Port 1
i/o bit 6 of Port 1
i/o bit 7 of Port 1
i/o Drive Voltage, +5 Vcc
Signal Descriptions
Vss
Circuit ground potential.
VDD
+5V power supply during operation.
PORT 1
Port 1 is an 8-bit quasi-bidirectional I/O port.
There is a pull-up resistance when operating at either
input or output.
PORT 3
Port 3 is an 7-bit quasi-bidirectinal I/O port. It also
contains the interrupt and timer as well as serial port
pins that are used by various options. The output latch
corresponding to a secondary function must be
programmed to one (1) for that function to operate.
The secondary functions are assigned to the pins of port
3, as follows:
- RXD/data (P3.0). Serial port's transmitter data input
(asynchronous) or data input/output (asynchronous).
- TXD/clock (P3.1). Serial port's transmitter data output
(asynchronous) or data input/output (asynchronous).
- #INT0 (P3.2). Interrupt 0 input or gate control input
for counter 0.
- #INT1 (P3.3). Interrupt 1 input or gate control input
for counter 1.
- T0 (P3.4). Input to counter 0.
- T1 (P3.5). Input to counter 1.
There is a pull-up resistance when operating at either
input or output.
RES
A low to high transition on this pin (V IH1) while the
oscillator is not running resets the MV20556. Holding
high signal (higher than V IH1) on this pin for two
machine cycles (24 clocks) or longer while the oscillator
is running, resets the device.
XTAL 1
Input to the oscillator's high gain amplifier. A crystal or
external source can be used.
XTAL 2
Output from the oscillator's amplifier. Required when a
crystal is used.
Specifications subject to change without notice, contact your sales representatives for the most recent information.
3/27
PID256** 07/97


3Pages


MV20556 電子部品, 半導体
MOSEL VITELIC INC.
Preliminary
MV20556
Memory Map Details
Internal RAM
The MV20556 contains a 128-byte Internal Data RAM
(Which includes registers R7-R0 in each of four Banks),
and twenty memory-mapped Special Function
Registers.
Internal Data RAM
The Internal Data RAM provides a convenient 128-byte
scratch pad memory.
128 Addressable Bits
There are 128 addressable software flags in the
Internal Data RAM. They are located in the 16 byte
locations starting at byte address 32 and ending with
byte location 47 of the RAM address space.
Stack
The stack may be located anywhere within the Internal
Data RAM address space. The stack may be as large
as 128 bytes on the MV20556.
Register Banks
There are four Register Banks within the Internal Data
RAM. Each Register Bank contains registers R7-R0.
7Fh
RAM
BYTE (MSB)
7FH
(LSB)
127
2FH 7F 7E 7D 7C 7B 7A 79 78 47
2EH 77 76 75 74 73 72 71 70 46
2DH 6F 6E 6D 6C 6B 6A 69 68 45
2CH 67 66 65 64 63 62 61 60 44
2BH 5F 5E 5D 5C 5B 5A 59 58 43
2AH 57 56 55 54 53 52 51 50 42
29H 4F 4E 4D 4C 4B 4A 49 48 41
28H 47 46 45 44 43 42 41 40 40
27H 3F 3E 3D 3C 3B 3A 39 38 39
26H 37 36 35 34 33 32 31 30 38
25H 2F 2E 2D 2C 2B 2A 29 28 37
24H 27 26 25 24 23 22 21 20 36
23H 1F 1E 1D 1C 1B 1A 19 18 35
22H 17 16 15 14 13 12 11 10 34
21H 0F 0E 0D 0C 0B 0A 09 08 33
20H 07 06 05 04 03 02 01 00 32
1FH
18H Bank 3
31
23
17H 24
Bank 2
10H
16
0FH 15
Bank 1
08H
8
07H 7
Bank 0
00H
0
scratch
pad
area
30h
2Fh
bit
addressable
area
RS1 RS0
R7
11
R0
R7
10
R0
R7
01
R0
R7
00
R0
20h
1Fh
18h
17h
Four
10h
0Fh
bank
area
08h
07h
00h
128B RAM Bit Address
128B RAM Memory Map
Specifications subject to change without notice, contact your sales representatives for the most recent information.
6/27
PID256** 07/97

6 Page



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部品番号部品説明メーカ
MV20556

8 - Bit MCU Mouse Controller

Mosel Vitelic
Mosel Vitelic


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