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HD6433044 の電気的特性と機能

HD6433044のメーカーはHitachi Semiconductorです、この部品の機能は「(HD64 Series) Hitachi Single-Chip Microcomputer」です。


製品の詳細 ( Datasheet PDF )

部品番号 HD6433044
部品説明 (HD64 Series) Hitachi Single-Chip Microcomputer
メーカ Hitachi Semiconductor
ロゴ Hitachi Semiconductor ロゴ 




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HD6433044 Datasheet, HD6433044 PDF,ピン配置, 機能
Hitachi Single-Chip Microcomputer
H8/3048 Series
H8/3048
HD64F3048, HD6473048, HD6433048
H8/3047
HD6433047
H8/3045
HD6433045
H8/3044
HD6433044
Hardware Manual
ADE-602-073B

1 Page





HD6433044 pdf, ピン配列
Contents
Section 1 Overview...................................................................................................... 1
1.1 Overview......................................................................................................................... 1
1.2 Block Diagram................................................................................................................ 5
1.3 Pin Description ............................................................................................................... 6
1.3.1 Pin Arrangement............................................................................................. 6
1.3.2 Pin Assignments in Each Mode...................................................................... 7
1.3.3 Pin Functions .................................................................................................. 10
Section 2 CPU ............................................................................................................... 15
2.1 Overview......................................................................................................................... 15
2.1.1 Features........................................................................................................... 15
2.1.2 Differences from H8/300 CPU ....................................................................... 16
2.2 CPU Operating Modes.................................................................................................... 17
2.3 Address Space................................................................................................................. 18
2.4 Register Configuration.................................................................................................... 19
2.4.1 Overview......................................................................................................... 19
2.4.2 General Registers............................................................................................ 20
2.4.3 Control Registers ............................................................................................ 21
2.4.4 Initial CPU Register Values ............................................................................ 22
2.5 Data Formats................................................................................................................... 23
2.5.1 General Register Data Formats....................................................................... 23
2.5.2 Memory Data Formats .................................................................................... 25
2.6 Instruction Set................................................................................................................. 26
2.6.1 Instruction Set Overview ................................................................................ 26
2.6.2 Instructions and Addressing Modes................................................................ 27
2.6.3 Tables of Instructions Classified by Function................................................. 28
2.6.4 Basic Instruction Formats ............................................................................... 38
2.6.5 Notes on Use of Bit Manipulation Instructions .............................................. 39
2.7 Addressing Modes and Effective Address Calculation .................................................. 39
2.7.1 Addressing Modes .......................................................................................... 39
2.7.2 Effective Address Calculation ........................................................................ 42
2.8 Processing States ............................................................................................................ 46
2.8.1 Overview......................................................................................................... 46
2.8.2 Program Execution State ................................................................................ 47
2.8.3 Exception-Handling State............................................................................... 47
2.8.4 Exception-Handling Sequences ...................................................................... 49
2.8.5 Bus-Released State ......................................................................................... 50
2.8.6 Reset State ...................................................................................................... 50
2.8.7 Power-Down State .......................................................................................... 50


3Pages


HD6433044 電子部品, 半導体
6.3.6 Interconnections with Memory (Example)..................................................... 139
6.3.7 Bus Arbiter Operation..................................................................................... 141
6.4 Usage Notes .................................................................................................................... 144
6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM ................................ 144
6.4.2 Register Write Timing .................................................................................... 144
6.4.3 BREQ Input Timing........................................................................................ 144
6.4.4 Transition to Software Standby Mode ............................................................ 146
Section 7 Refresh Controller .................................................................................... 147
7.1 Overview......................................................................................................................... 147
7.1.1 Features........................................................................................................... 147
7.1.2 Block Diagram................................................................................................ 148
7.1.3 Input/Output Pins............................................................................................ 149
7.1.4 Register Configuration.................................................................................... 149
7.2 Register Descriptions...................................................................................................... 150
7.2.1 Refresh Control Register (RFSHCR) ............................................................. 150
7.2.2 Refresh Timer Control/Status Register (RTMCSR) ....................................... 153
7.2.3 Refresh Timer Counter (RTCNT)................................................................... 155
7.2.4 Refresh Time Constant Register (RTCOR) .................................................... 155
7.3 Operation ........................................................................................................................ 156
7.3.1 Overview......................................................................................................... 156
7.3.2 DRAM Refresh Control.................................................................................. 157
7.3.3 Pseudo-Static RAM Refresh Control.............................................................. 172
7.3.4 Interval Timing ............................................................................................... 177
7.4 Interrupt Source .............................................................................................................. 183
7.5 Usage Notes .................................................................................................................... 183
Section 8 DMA Controller ........................................................................................ 185
8.1 Overview......................................................................................................................... 185
8.1.1 Features........................................................................................................... 185
8.1.2 Block Diagram................................................................................................ 186
8.1.3 Functional Overview....................................................................................... 187
8.1.4 Input/Output Pins............................................................................................ 188
8.1.5 Register Configuration.................................................................................... 188
8.2 Register Descriptions (Short Address Mode) ................................................................. 190
8.2.1 Memory Address Registers (MAR)................................................................ 190
8.2.2 I/O Address Registers (IOAR)........................................................................ 191
8.2.3 Execute Transfer Count Registers (ETCR)..................................................... 191
8.2.4 Data Transfer Control Registers (DTCR) ....................................................... 193
8.3 Register Descriptions (Full Address Mode) ................................................................... 196
8.3.1 Memory Address Registers (MAR)................................................................ 196

6 Page



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共有リンク

Link :


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