PDF ST72T734 Data sheet ( Hoja de datos )

Número de pieza	ST72T734
Descripción	(ST72T774 - ST72T734) 8-BIT USB MCU FOR MONITORS
Fabricantes	ST Microelectronics
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ST72774/ST72754/ST72734 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C s User ROM/OTP/EPROM: up to 60 Kbytes s Data RAM: up to 1 Kbytes (256 bytes stack) s 8 MHz Internal Clock Frequency in fast mode, 4 MHz in normal mode s Run and Wait CPU modes s System protection against illegal address jumps and illegal opcode execution s Sync Processor for Mode Recognition, power management and composite video blanking, clamping and free-running frequency generation – Corrector mode – Analyzer mode s USB (Universal Serial Bus) for monitor function 1 – Three endpoints – Integrated 3.3V voltage regulator – Transceiver – Suspend and Resume operations s Timing Measurement Unit (TMU) autoposition and autosize 1 s Fast I2C Single Master Interface for s DDC Bus Interface with: – DDC1/2B protocol implemented in hardware – Programmable DDC CI modes – Enhanced DDC (EDDC) address decoding PSDIP42 TQFP44 10 x 10 s 2 lines programmable as interrupt inputs s 16-bit timer with 2 input captures and 2 output compare functions s 8-bit Analog to Digital Converter with 4 channels on port B s 8 10-bit PWM/BRM Digital to Analog outputs s Master Reset and Low Voltage Detector (LVD) reset s Programmable Watchdog for system reliability s Fully static operation s 63 basic instructions / 17 main addressing modes s 8x8 unsigned multiply instruction s True bit manipulation s Complete development support on PC/DOS- Windows: Real-Time Emulator, EPROM Programming Board and Gang Programmer s 31 I/O lines s Full software package (assembler, linker, C- compiler, source level debugger) Device Summary Features ST72(T/E)774(J/S)9 ST72(T)754(J/S)9 ST72774(J/S)7 ST72754(J/S)7 ST72(T/E)734J6 Program Memory - Bytes 60K 48K 32K RAM (stack) - Bytes 1K (256) 512 (256) Peripherals USB No USB USB No USB ADC 3, 16-bit timer, I2C, DDC, TMU,Sync, PWM, LVD, Watchdog No USB ADC4, I2C,LVD, DDC,Sync, 16-bit timer, PWM, Watchdog Operating Supply 4.0V to 5.5V supply operating range Oscillator Frequency 12 or 24 MHz Operating Temperature 0 to +70°C Package CSDIP42 or PSDIP42 or TQFP44 PSDIP42 CSDIP42 (1) On some devices only, refer to Device Summary; (2) Contact Sales office for availability (3) 8-bit ±2 LSB A/D converter ; (4) 8-bit ±4 LSB A/D converter. October 2003 1/144 1 1 page Revision follow-up ST72774/ST727754/ST72734 Changes applied since version 4.0 Version 4.0 Version 4.1 Version 4.2 Version 4.3 Version 4.3 March 2001 Page 1:Addition of 72T774 (32KOTP). Addition of 60K/48K ROM for ST72754 Deletion of table “ device summary”, replaced with cross reference to table 36 on page 147. page 13 - addition of section 1.4. external connections July 2001 Initial format reapplied, text and related figures in the same page. Table “Device summary” reinserted in cover page and updated. Update of table 36: ordering information (p143) July 2001 Cover - addition of feature about system protection added, table for device summary: addition of stack values page 9 - figure 3: replaced 1KByte with 512 Bytes + notes about opcode fetch and HALT mode page 10 - table: CR replaced by WDGCR TIM replaced with Timer and WDG replaced with Watchdog page 115 - EDF register: addition of “read from RAM”, EDE: few changes page 135 - Note 1 replaced, note 2 added SUSpend mode limitation.. Whole document: all mentions of HALT mode either deleted or rewritten. October 2001 p140, chapter 8, section 8.1- code for unused bytes ( FFh) replaced with 9Dh (opcode for NOP) page 141- update of table 36 “Ordering information” page 142 - list of available devices updated page 114 - DDC DCR register: bit 5 = 1, text “or read from RAM” deleted November 2001 page 10, one adddress corrected in the figure 3 “memory map”: 0400h page 14: addition of mandatory 1K resistor (text and figure) 5/144 3 5 Page MEMORY MAP (Cont’d) ST72774/ST727754/ST72734 Table 2. Hardware Register Memory Map Address Block Register Label Register Name 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 00010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h to 0024h Watchdog ADC DDC1/2B TMU Timer PADR PADDR PBDR PBDDR PCDR PCDDR PDDR PDDDR WDGCR MISCR ADCDR ADCCSR DDCDCR DDCAHR TMUCSR TMUT1CR TMUT2CR TIMCR2 TIMCR1 TIMSR TIMIC1HR TIMIC1LR TIMOC1HR TIMOC1LR TIMCHR TIMCLR TIMACHR TIMACLR TIMIC2HR TIMIC2LR TIMOC2HR TIMOC2LR Port A Data Register Port A Data Direction Register Port B Data Register Port B Data Direction Register Port C Data Register Port C Data Direction Register Port D Data Register Port D Data Direction Register Watchdog Control Register Miscellaneous Register ADC Data Register ADC Control Status register DDC1/2B Control Register DDC1/2B Address Pointer High Register TMU control status register TMU T1 counter register TMU T2 counter register Timer Control Register 2 Timer Control Register 1 Timer Status Register Timer Input Capture 1 High Register Timer Input Capture 1 Low Register Timer Output Compare 1 High Register Timer Output Compare 1 Low Register Timer Counter High Register Timer Counter Low Register Timer Alternate Counter High Register Timer Alternate Counter Low Register Timer Input Capture 2 High Register Timer Input Capture 2 Low Register Timer Output Compare 2 High Register Timer Output Compare 2 Low Register Reserved Area (5 bytes) Reset Status 00h 00h 00h 00h 00h 00h 00h 00h 7Fh 10h 00h 00h 00h xxh FCh FFh FFh 00h 00h 00h xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read only R/W R/W R/W R/W Read only Read only R/W R/W Read only Read only Read only R/W R/W Read only R/W Read only R/W Read only Read only R/W R/W 11/144 11 Page

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