PDF ST72T85C Data sheet ( Hoja de datos )

Número de pieza	ST72T85C
Descripción	8-BIT MCU FOR RDS WITH 48K ROM
Fabricantes	ST Microelectronics
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R ST7285C 8-BIT MCU FOR RDS WITH 48K ROM, 3 K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES s 4.5V to 5.5V Supply Operating Range s Operates at 8.664MHz Oscillator Frequency for RDS compatibility s Fully Static operation s -40°C to + 85°C Maximum Operating Temperature Range s Run, Wait, Slow, Halt and RAM Retention modes s User ROM: 48 Kbytes s Data RAM: 3 Kbytes, including 128 byte stack s 80 pin plastic package s 62 multifunctional bidirectional I/O lines: – Programmable Interrupt inputs on some I/Os – 8 Analog inputs – EMI filtering s Two 16-bit Timers, each featuring: – 2 Input Captures – 2 Output Compares – External Clock input (on Timer A) – PWM and Pulse Generator modes s RDS Radio Data System Filter, Demodulator and GBS circuits s 8-bit Analog-to-Digital converter with 8 channel analog multiplexer s Digital Watchdog s Two SPI Serial Peripheral Interfaces s SCI Serial Communications Interface s Full I2C multiple Master/ Slave interface s 2KHz Beep signal generator s Master Reset and Power-On Reset s 8-bit Data Manipulation s 63 Basic Instructions s 17 main Addressing Modes s 8 x 8 Unsigned Multiply Instruction s True Bit Manipulation s Complete Development Support on PC/DOS/ WindowsTM Real-Time Emulator s Full Software Package (C-Compiler, Cross- Assembler, Debugger) November 1997 PQFP80 Rev. 1.0 1/117 1 1 page ST7285C 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST7285C HCMOS Microcontroller Unit is a member of the ST7 family of Microcontrollers ded- icated to car radio applications with RDS capabili- ty. The device is based on an industry-standard 8- bit core and features an enhanced instruction set. The device is normally operated at an 8.664MHz oscillator frequency for RDS compatibility but, thanks to the fully static design, operation is possi- ble down to DC, when RDS functionality is not re- quired. Under software control, theST7285C may be placed in either WAIT, SLOW or HALT modes, thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8- bit data management, the ST7285C features true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. Figure 1. ST7285C Block Diagram The device includes an on-chip oscillator, CPU, ROM, RAM, 62 I/O lines and the following on-chip peripherals: Analog-to-Digital converter (ADC), two industry standard SPI serial interfaces, a Seri- al Communications Interface, an I2C interface, a digital Watchdog Timer, two independent 16-bit Timers, one featuring an External Clock Input, and both featuring Pulse Generator capabilities, 2 In- put Captures and 2 Output Compares. RDS Filter, Demodulator and GBS circuitry for car radio appli- cations is also included. NOTE: FOR THIS DEVICE, SGS-THOMSON CAN ONLY RECEIVE MOTOROLA S19 FORMAT FOR ROM CODES. RDScomp RDS fil RDS ref MPX OSCin OSCout RESET ARS AINT VPP / TEST PH0 - PH5 Pin 53..58 PG0 - PG7 Pin 45..52 6 8 RDS FILTER,DEMOD,GBS OSC Internal CLOCK 8 -BIT CORE ALU Power on Reset Watchdog ROM or EPROM* 48k RAM 3k PORT H PORT G PORT A A/D Converter SCI PORT B Timer A Timer B PORT C SPI B SPI A PORT D I2C PORT E PORT F VDD VSS *On EPROM or OTP versions only. 22 VDDP VSSP VDDA VSSA 8 PA0 - PA7 8 Pin 65..72 2 8 PB0 - PB7 Pin 73..80 4 8 PC0 - PC7 Pin 5..12 4 4 8 PD0 - PD7 Pin 13..20 2 8 PE0 - PE7 Pin 25..32 8 PF0 - PF7 Pin 33..40 VR01735P 5/117 5 Page ST7285C Address 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh Block I2C Timer A Timer B SCI SCI Prescaler RDS Filter Register name CR: Control Register SR1: Status Register 1 SR2: Status Register 2 CCR: Clock Control Register OAR1: Own Address Register 1 OAR2: Own Address Register 2 DR: Data Register Reset Status 00h 00h 00h 00h 00h 00h 00h Remarks R/W Register Read Only Register Read Only Register R/W Register R/W Register R/W Register R/W Register RESERVED Control Reg2 Control Reg1 Status Reg Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low RegisteR Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register RESERVED Control Reg2 Control Reg1 Status Reg Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register SCSR: Status Register SCDR: Data Register SCBRR: Baud Rate Register SCCR1: Control Register 1 SCCR2: Control Register 2 PSCBRR: Receive Baud Rate Reg Reserved PSCBRT: Transmit Baud Rate Reg RESERVED RESERVED RDS FI1 RDS FI2 00h 00h XXh XXh XXh XXh XXh FFh FCh 00h 00h XXh XXh XXh XXh 00h 00h XXh XXh XXh XXh XXh FFh FCh 00h 00h XXh XXh XXh XXh 1100000xb XXh 00x----xb XXh 00h 00h --- 00h R/W Register R/W Register Read Only Register Read Only Register Read Only Register R/W Register R/W Register Read Only Register Read Only Register Read Only Register Read Only Register Read Only Register Read Only Register R/W Register R/W Register R/W Register R/W Register Read Only Register Read Only Register Read Only Register R/W Register R/W Register Read Only Register Read Only Register Read Only Register Read Only Register Read Only Register Read Only Register R/W Register R/W Register Read Only Register R/W Register R/W Register R/W Register R/W Register R/W Register Reserved ST use R/W Register R/W Register R/W Register 11/117 11 Page

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