|
|
PDF 25020AN Data sheet ( Hoja de datos )
| Número de pieza | 25020AN | |
| Descripción | AT25040A | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 25020AN (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
|
No Preview Available !
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Data Sheet Describes Mode 0 Operation
• Medium-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
• Extended Temperature Range −40°C to +125°C
• 5.0 MHz Clock Rate
• 8-byte Page Mode
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
• Self-timed Write Cycle (10 ms max)
www.DataS•heHeitg4hU.Rcoemliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP Packages
Description
The AT25010A/020A/040A provides 1024/2048/4096 bits of serial electrically-eras-
able programmable read-only memory (EEPROM) organized as 128/256/512 words of
8 bits each. The device is optimized for use in many automotive applications where
low-power and low-voltage operation are essential. The AT25010A/020A/040A is
available in space-saving 8-pin PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP
packages.
The AT25010A/020A/040A is enabled through the Chip Select pin (CS) and accessed
via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO),
and Serial Clock (SCK). All programming cycles are completely self-timed, and no
separate erase cycle is required before write.
Block write protection is enabled by programming the status register with one of four
blocks of write protection. Separate program enable and program disable instructions
are provided for additional data protection. Hardware data protection is provided via
the WP pin to protect against inadvertent write attempts. The HOLD pin may be used
to suspend any serial communication without resetting the serial sequence.
Table 1. Pin Configurations
8-lead PDIP
Pin Name
CS
SCK
Function
Chip Select
Serial Data Clock
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
SI
SO
GND
VCC
WP
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
8-lead SOIC
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
HOLD
Suspends Serial Input
8-lead TSSOP
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
SPI Serial
Extended
Temperature
EEPROMs
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
AT25010A
AT25020A
AT25040A
5087B–SEEPR–1/05
1
1 page  
Serial Interface
Description
www.DataSheet4U.com
AT25010A/020A/040A
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the
AT25010A/020A/040A always operates as a slave.
TRANSMITTER/RECEIVER: The AT25010A/020A/040A has separate pins designated
for data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
The op-code also contains address bit A8 in both the Read and Write instructions.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25010A/020A/040A, and the serial output pin (SO) will remain in a high impedance
state until the falling edge of CS is detected again. This will reinitialize the serial
communication.
CHIP SELECT: The AT25010A/020A/040A is selected when the CS pin is low. When
the device is not selected, data will not be accepted via the SI pin, and the serial output
pin (SO) will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the
AT25010A/020A/040A. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low, all write operations are inhibited. WP
going low while CS is still low will interrupt a write to the AT25010A/020A/040A. If the
internal write cycle has already been initiated, WP going low will have no effect on any
write operation.
5087B–SEEPR–1/05
5
5 Page 
Figure 8. READ Timing
AT25010A/020A/040A
www.DataSheet4U.com
Figure 9. WRITE Timing
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
INSTRUCTION
BYTE ADDRESS
DATA IN
SI 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
9TH BIT OF ADDRESS
HIGH IMPEDANCE
SO
HOLD Timing
CS
SCK
HOLD
SO
t CD
t HD
t HZ
t CD
t HD
t LZ
5087B–SEEPR–1/05
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet 25020AN.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 25020AN | AT25040A | ATMEL Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |