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IS28F020 の電気的特性と機能

IS28F020のメーカーはIntegrated Silicon Solutionです、この部品の機能は「262144 x 8 CMOS Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS28F020
部品説明 262144 x 8 CMOS Flash Memory
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS28F020 Datasheet, IS28F020 PDF,ピン配置, 機能
IS28F020
IS28F020
262,144 x 8 CMOS FLASH MEMORY
ISISSSII®®
FEBRUARY 1997
FEATURES
• High performance
- 50 ns maximum access time
• CMOS low power consumption
- 30 mA maximum active current
- 100 µA maximum standby current
• Compatible with JEDEC-standard byte-wide
pinouts
- 32-pin DIP
- 32-pin PLCC
- 32-pin TSOP
• Program and erase voltage 12.0V ± 5%
• Maximum latch-up immunity through
advanced CMOS process
BLOCK DIAGRAM
• Flash electrical bulk chip-erase
- One second typical chip-erase
• Fast-pulse programming algorithm
- 10 µs (typical) byte-program
- 4 second chip-program
• Command register architecture for micro-
processor/microcontroller compatible write
interface
• On-chip address and data latches for
programming
• Advanced CMOS flash memory technology
- Low cost single transistor memory cell
• Integrated program/erase stop timer
DQ7-D0
VCC
GND
VPP
WE
OE
CE
STATE
CONTROL
COMMAND
REGISTER
INTEGRATED
STOP TIMER
ERASE VOLTAGE
SWITCH
TO ARRAY
PROGRAM VOLTAGE
SWITCH
CHIP ENABLE/
OUTPUT ENABLE
LOGIC
INPUT/OUTPUT
BUFFERS
DATA
LATCH
LOW VOLTAGE
DETECTOR
Y-DECODER
Y-GATING
A0-A17
X-DECODER
2,097,152
CELL
MATRIX
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1996, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
Rev. F 2/04/97
FL81995SEC20
1

1 Page





IS28F020 pdf, ピン配列
IS28F020
PRINCIPLES OF OPERATION
ISSI’s IS28F020 flash memory augments EPROM func-
tionality with in-circuit electrical erasure and reprogram-
ming. The IS28F020 uses a command register to manage
this functionality. The command register allows for 100%
TTL-level control inputs and fixed power supply levels
during erasure and programming, while maintaining maxi-
mum EPROM compatibility.
With the Vpp pin at a low voltage level, the IS28F020 is a
read-only memory. With the Vpp pin at a high voltage level,
the same EPROM read, standby, and output disable
operations are available along with enabling erasure and
programming operations. All functions associated with
altering memory contents—ISSI identifier, erase, erase
verify, program, and program verify—are accessed via the
command register.
Command codes are written to the command register
using standard microprocessor write timings. Contents of
the command register serve as instruction codes input to
an internal state-machine which controls the erase and
programming circuitry. With the appropriate command
codes written to the register, standard microprocessor
read timings may output array data, access the ISSI
identifier codes, or output data for erase and program
verification. Table 2 defines these IS28F020 command
codes.
Integrated Stop Timer
The program or erase time durations are normally termi-
nated by associated program or erase verify commands.
An integrated stop timer provides simplified timing control
over these operations; thus eliminating the need for maxi-
mum program/erase timing specifications. Programming
and erase pulse durations are minimums only. When the
stop timer terminates a program or erase operation, the
device enters an inactive state and remains inactive until
receiving the appropriate verify or reset command.
Write Protection
The IS28F020 uses a two-step program/erase write se-
quence to the command register which provides additional
software write protections. The command register is active
when VPP = VPPH. When VPP = VPPL, the contents of the
command register default to 00H, making the IS28F020 a
read-only memory. The system designer may choose to
make the VPP power-supply switchable or to “hardwire”
VPP = VPPH. The IS28F020 is designed to accommodate
either design practice, and to encourage optimization of
the processor-memory interface.
ISSI ®
BUS OPERATIONS
Read
The IS28F020 has CE and OE control signals. To obtain
data at the output, both control signals must be brought
low. Chip-Enable (CE) is used for device selection. Out-
put-Enable (OE) is used to gate data from the output pins,
when the device is selected by asserting CE LOW. Refer
to AC read timing waveforms.
When VPP is HIGH (VPPH), the read operation can be used
to access array data, to output the ISSI identifier codes,
and to access data for program/erase verification. When
VPP is LOW (VPPL), the read operation can only access the
array data.
Output Disable
When OE is HIGH (VIH), device output is disabled. The
output pins are placed in a high-impedance state.
Standby
When CE is HIGH, the standby operation disables most of
the IS28F020’s circuitry and substantially reduces device
power consumption. The outputs are placed in a high-
impedance state, independent of the Output Enable sig-
nal. If the IS28F020 is deselected during erasure, pro-
gramming, or program/erase verification, the device draws
active current until the operation is terminated.
ISSI Identifier Operation
The ISSI identifier operation outputs the manufacturer
code (D5H) and device code (B4H). Programming equip-
ment automatically matches the device with its proper
erase and programming algorithms.
With CE and OE both LOW, raising A9 to high voltage, VID
activates the ISSI identifier operation. Data read from
locations 0000H and 0001H represent the manufacturer’s
code and the device code, respectively.
The manufacturer code and device code can also be read
via the command register, for example, when the IS28F020
is erased and reprogrammed in the target system. Follow-
ing a write of 90H to the command register, a read from
address location 0000H outputs the manufacturer code
(D5H). A read from address 0001H outputs the device
code (BDH).
Integrated Silicon Solution, Inc.
Rev. F 2/04/97
FL81995SEC20
3


3Pages


IS28F020 電子部品, 半導体
IS28F020
Setup Program/Program Commands (40H)
The setup program operation is initiated by writing 40H to
the command register. It is a command-only operation that
instructs the device for byte programming. Once the setup
program operation is performed, the next Write-Enable
pulse causes a transition to an active programming opera-
tion. Addresses are internally latched on the falling edge of
the Write-Enable pulse. Data is internally latched on the
rising edge of Write-Enable pulse. The rising edge of
Write-Enable also begins the programming operation. The
IS28F020 is programmed on a byte-by-byte basis. Byte
programming may occur sequentially or at random. The
programming operation terminates with the next rising
edge of Write-Enable that used to write the program-verify
command. Refer to AC Programming Characteristics and
Waveforms for specific timing parameters.
Program-Verify Command (C0H)
Following each programming operation, the byte just
programmed must be verified.
The program-verify operation is initiated by writing C0H to
the command register. It instructs the device for verifica-
tion of the byte last programmed. The IS28F020 applies an
internally-generated margin voltage to the byte. A stan-
dard microprocessor read cycle may output the data. If a
comparison between the programmed byte and the true
data is successful, programming then proceeds to the next
desired byte location. Figure 1, the IS28F020 Fast-Pulse
programming algorithm, illustrates how commands are
combined with bus operations to perform byte program-
ming. Refer to AC Programming Characteristics and Wave-
forms for specific timing parameters.
Reset Command (FFH)
A reset command is used to abort the erase- or program-
command sequences safely . Following either setup erase
operation or setup program operation with two consecu-
tive writes of FFH will safely abort the operation. Memory
contents will not be altered. A valid command must then be
written to place the device in the desired state.
ERASE/PROGRAM CYCLING
The IS28F020 is programmed and erased using ISSI’s
Fast-Pulse programming and Fast-Erase algorithms. The
algorithmic approach uses a series of pulses, along with
byte verification, to completely and reliably erase and
program the device.
ISSI ®
FAST-PULSE PROGRAMMING ALGORITHM
The IS28F020 is programmed on a byte-by-byte basis
using 10 µs duration programming pulse in accordance
with ISSI’s Fast-Pulse programming algorithm. Each op-
eration is followed by a byte verification to determine when
the addressed byte has been successfully programmed.
The algorithm allows for up to 25 programming operations
per byte, although most bytes verify on the first or second
operation. The entire sequence of programming and byte
verification is performed with VPP at high voltage. Figure 1
illustrates the Fast-Pulse Programming algorithm.
FAST-ERASE ALGORITHM
The erase operation erases all bytes of the array in
parallel. The entire device is bulk erased using 10 ms
duration erase pulse in accordance with ISSI’s Fast-Erase
algorithm. The Fast-Erase algorithm yields fast and reli-
able electrical erasure of memory contents. The algorithm
employs a Fowler-Nordheim tunneling to simultaneously
remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
IS28F020 is erased when shipped from the factory. Read-
ing FFH data from the device would immediately be
followed by device programming.
For devices being erased and reprogrammed, uniform and
reliable erasure is ensured by first programming all bits in
the device to their charged state (Data=00H). This is
accomplished, using the Fast-Pulse Programming algo-
rithm, in approximately two seconds.
Erase execution then continues with an initial erase opera-
tion. Erase verification (Data=FFH) begins at address
0000H and continues through the array to the last address,
or until data other than FFH is encountered. With each
erase operation, an increasing number of bytes verify to
the erased state. Erase efficiency may be improved by
storing the address of the last byte verified in a register.
Following the next erase operation, verification starts at
that stored address location. Erasure typically occurs in
one second. Figure 2 illustrates the Fast-Erase algorithm.
6 Integrated Silicon Solution, Inc.
Rev. F 2/04/97
FL81995SEC20

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
IS28F020

262144 x 8 CMOS Flash Memory

Integrated Silicon Solution
Integrated Silicon Solution
IS28F020BL

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IS28F020BLV

262144 x 8 SmartVoltage Boot Block Flash Memory

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