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PDF 23C256 Data sheet ( Hoja de datos )
| Número de pieza | 23C256 | |
| Descripción | HT23C256 | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 23C256 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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HT23C256
CMOS 32K×8-Bit Mask ROM
Features
• Operating voltage 2.7V~5.5V
• Low power consumption
– Operation: 25mA max. (VCC=5V)
10mA max. (VCC=3V)
– Standby: 30µA max. (VCC=5V)
10µA max. (VCC=3V)
• Access time:150ns max. (VCC=5V)
250ns max. (VCC=3V)
General Description
The HT23C256 is a read-only memory with
high performance CMOS storage device whose
256K of memory is arranged into 32768 words
by 8 bits.
For application flexibility, the chip enable and
output enable control pins can be selected as
active high or active low. This flexibility not
only allows easy interface with most microproc-
• 32768×8 bits of mask ROM
• Mask options: chip enable CE/CE/OE1/OE1 and
output enable OE/OE/NC
• TTL compatible inputs and outputs
• Tristate outputs
• Fully static operation
• Package type: 28-pin DIP/SOP
essors, but also eliminates bus contention in
multiple bus microprocessor systems. An addi-
tional feature of the HT23C256 is its ability to
enter the standby mode whenever the chip en-
able (CE/CE) is inactive, thus reducing current
consumption to below 30µA. The combination of
these functions makes the chip suitable for high
density low power memory applications.
Block Diagram
1 24th Aug ’98
1 page  
A.C. test conditions
Output load: see figure right
Input rise and fall time: 10ns
Input pulse levels: 0.4V to 2.4V
Input and output timing reference levels:
0.8V and 2.0V (VCC=5V), 1.5V (VCC=3V)
HT23C256
Output load circuit
Functional Description
The HT23C256 has two modes, namely data
read mode and standby mode, controlled by
CE/CE/OE1/OE1 and OE/OE/NC inputs.
• Standby mode
The HT23C256 has lower current consumption,
controlled by the chip enable input (CE/CE).
When a low/high level is applied to the CE/CE
input regardless of the output enable
(OE/OE/NC) states the chip will enter the
standby mode.
• Data read mode
When both the chip enable (CE/CE/OE/OE1)
and the output enable (OE/OE/NC) are active,
the chip is in data read mode. Otherwise,
active CE/CE and inactive OE/OE/NC result
in deselect mode. The output will remain in
Hi-Z state.
Timing Diagrams
• Propagation delay due to address (CE/CE/OE1/OE1 and OE/OE are active)
• Propagation delay due to chip enable and output enable (address valid)
5 24th Aug ’98
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 23C256.PDF ] | |
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