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PDF HD64465 Data sheet ( Hoja de datos )
| Número de pieza | HD64465 | |
| Descripción | Intelligent Peripheral Controller | |
| Fabricantes | Hitachi | |
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Hay una vista previa y un enlace de descarga de HD64465 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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Windows® CE Intelligent Peripheral Controller
HD64465
User’s Manual
ADE-602-168B
Rev. 3.0
03/08/01
Hitachi Ltd.
1 page  
Page Item
Description
152 (26) Timing control Register Delete the default value
(ITMCR)
Bits 5 - 0
176 (2) ECP Address FIFO Register Default value of bits 2 - 0
(ECPAFifo)
<Former Edition> 111b
<This Edition> 111
(4) Device Control Register (der) Default value of bits 2 - 0
(Address H’1000A004, Mode All) <Former Edition> 11b
<This Edition> 11
227 Table 14.3 AC97 Timing
<Former Edition> Unit : Us
Ns
<This Edition> Unit : µs
ns
336 19.2.1 A/D Data Registers A to D <Former Edition> Bit 9 : AD8
(ADDRA to ADDRD, ADCAL)
Bit 8 : AD9
<This Edition> Bit 9 : AD9
Bit 8 : AD8
341 19.3.2 Acan Mode (SCAN = 1) Add the ADCSR table
352, 353 Table 20.13 AFECK clock input New tables added
AC Timing Spec. (PLL1:bypass)
(unit : ns)
Table 20.14 AFECK clock input
AC Timing Spec.
(PLL1:operatings) (unit : ns)
Table 20.15 AFECK clock input
AC Timing Spec. (PLL2:bypass)
(unit : ns)
Table 20.16 AFECK clock input
AC Timing Spec.
(PLL2:operating) (unit : ns)
363, 364 Figure 20.26 AFECK Clock Input New figures added
Timing
Figure 20.27 UCK Clock Input
Timing
5 Page 
14.2.2 Receive Data Register (RDR) ..............................................................................185
14.2.3 Control Register (CR) ..........................................................................................186
14.2.4 Status Register (SR) .............................................................................................187
14.2.5 Frequency Select Register ....................................................................................189
14.2.6 Command/Status Address Register (CSAR) ........................................................190
14.2.7 Command/Status Data Register (CSDR)..............................................................191
14.2.8 PCM Playback/Record Left Channel (PCML).....................................................192
14.2.9 PCM Playback/Record Right Channel (PCMR) ..................................................193
14.2.10 Line 1 Data Register (LINE1) ..............................................................................194
14.2.11 PCM Center Playback/MIC ADC Channel (PCMC) ...........................................195
14.2.12 PCM Left Surround Channel Data Register (PCMLS) ........................................196
14.2.13 PCM Right Surround Channel Data Register (PCMRS) ......................................197
14.2.14 PCMLFE Data Register (PCMLFE) ....................................................................198
14.2.15 Line 2 Channel Data Register (LINE2)................................................................199
14.2.16 HSET Data Register (HSET) ...............................................................................200
14.2.17 IO Control/Status Data Register (IOCS) ..............................................................201
14.2.18 AC97 Transmit Interrupt Enable Register (ATIER) ............................................202
14.2.19 AC97 TX FIFO Status Register ...........................................................................205
14.2.20 AC97 RX FIFO Interrupt Enable Register (ARIER) ...........................................208
14.2.21 AC97 RX Status Register (ARSR).......................................................................211
14.2.22 AC97 Control Register (ACR) .............................................................................213
14.2.23 AC97 TAG Register (ATAGR)............................................................................215
14.2.24 Slot Request Active Register (SRAR)..................................................................216
14.3 Function Description .........................................................................................................217
14.3.1 Internal Bus Interface ...........................................................................................217
14.3.2 Clock Generator ...................................................................................................217
14.3.3 CS4218 or CS4271 TX Controller .......................................................................218
14.3.4 CS4218 or CS4271 RX Controller .......................................................................218
14.3.5 AC97 TX Controller.............................................................................................218
14.3.6 AC97 RX Controller ............................................................................................219
14.3.7 Miscellaneous Function Block .............................................................................219
14.3.8 Data Structure of Memory in DMA Mode ...........................................................219
14.4 Program Flow....................................................................................................................220
Section 15 AFE Interface ..................................................................................229
15.1 Overview ...........................................................................................................................229
15.1.1 Features ................................................................................................................229
15.1.2 Block Diagram .....................................................................................................230
15.2 Register Description ..........................................................................................................231
15.2.1 Control Register (CTR) ........................................................................................232
15.2.2 Status Register (STR)...........................................................................................233
15.2.3 Transmit Data Register (TXDR) ..........................................................................236
15.2.4 Receive Data Register (RXDR)............................................................................236
Rev. 3.0, 03/01, page v of xiii
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet HD64465.PDF ] | |
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