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PDF HD6432351 Data sheet ( Hoja de datos )
| Número de pieza | HD6432351 | |
| Descripción | (HD6412350 / HD6432351) 16-BIT MICROCONTROLLER | |
| Fabricantes | Hitachi | |
| Logotipo |  |
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
Preface
The H8S/2350 Series is a series of high-performance microcontrollers with a 32-bit H8S/2000
CPU core, and a set of on-chip supporting functions required for system configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
On-chip memory consists of large-capacity ROM (H8S/2351 only) and RAM.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse
generator (PPG), watchdog timer (WDT), serial communication interface (SCI), A/D converter,
D/A converter, and I/O ports.
In addition, an on-chip DMA controller (DMAC) and data transfer controller (DTC) are provided,
enabling high-speed data transfer without CPU intervention.
Use of the H8S/2350 Series enables easy implementation of compact, high-performance systems
capable of processing large volumes of data.
This manual describes the hardware of the H8S/2350 Series. Refer to the H8S/2600 Series and
H8S/2000 Series Programming Manual for a detailed description of the instruction set.
5 Page 
6.10.2 Operation .............................................................................................................. 185
6.10.3 Pin States in External Bus Released State ............................................................ 186
6.10.4 Transition Timing ................................................................................................. 187
6.10.5 Usage Note............................................................................................................ 188
6.11 Bus Arbitration................................................................................................................... 188
6.11.1 Overview............................................................................................................... 188
6.11.2 Operation .............................................................................................................. 188
6.11.3 Bus Transfer Timing ............................................................................................. 189
6.11.4 External Bus Release Usage Note ........................................................................ 189
6.12 Resets and the Bus Controller............................................................................................ 190
Section 7 DMA Controller .............................................................................................. 191
7.1 Overview............................................................................................................................ 191
7.1.1 Features ................................................................................................................. 191
7.1.2 Block Diagram...................................................................................................... 192
7.1.3 Overview of Functions.......................................................................................... 193
7.1.4 Pin Configuration.................................................................................................. 195
7.1.5 Register Configuration.......................................................................................... 196
7.2 Register Descriptions (1) (Short Address Mode) .............................................................. 197
7.2.1 Memory Address Registers (MAR)...................................................................... 198
7.2.2 I/O Address Register (IOAR) ............................................................................... 199
7.2.3 Execute Transfer Count Register (ETCR)............................................................ 199
7.2.4 DMA Control Register (DMACR) ....................................................................... 200
7.2.5 DMA Band Control Register (DMABCR) ........................................................... 205
7.3 Register Descriptions (2) (Full Address Mode) ................................................................. 211
7.3.1 Memory Address Register (MAR)........................................................................ 211
7.3.2 I/O Address Register (IOAR) ............................................................................... 211
7.3.3 Execute Transfer Count Register (ETCR)............................................................ 212
7.3.4 DMA Control Register (DMACR) ....................................................................... 213
7.3.5 DMA Band Control Register (DMABCR) ........................................................... 217
7.4 Register Descriptions (3) ................................................................................................... 222
7.4.1 DMA Write Enable Register (DMAWER)........................................................... 222
7.4.2 DMA Terminal Control Register (DMATCR) ..................................................... 225
7.4.3 Module Stop Control Register (MSTPCR)........................................................... 226
7.5 Operation............................................................................................................................ 227
7.5.1 Transfer Modes ..................................................................................................... 227
7.5.2 Sequential Mode ................................................................................................... 230
7.5.3 Idle Mode.............................................................................................................. 233
7.5.4 Repeat Mode ......................................................................................................... 236
7.5.5 Single Address Mode............................................................................................ 240
7.5.6 Normal Mode........................................................................................................ 243
7.5.7 Block Transfer Mode............................................................................................ 246
7.5.8 DMAC Activation Sources ................................................................................... 252
v
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD6432351.PDF ] | |
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