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PDF HD64F36912G Data sheet ( Hoja de datos )
| Número de pieza | HD64F36912G | |
| Descripción | (HD64xxx Series) 16-BIT MICROCONTROLLER | |
| Fabricantes | Renesas Technology | |
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16 ,H8/36912 Group H8/36902 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8 Family/H8/300H Tiny Series
H8/36912F
H8/36902F
H8/36912
H8/36911
H8/36902
H8/36901
H8/36900
HD64F36912G
HD64F36902G
HD64336912G
HD64336911G
HD64336902G
HD64336901G
HD64336900G
Rev.1.00
2003.11.7
1 page  
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 1.00, 11/03, page v of xxviii
5 Page 
Section 6 Power-Down Modes ......................................................................... 83
6.1 Register Descriptions ........................................................................................................84
6.1.1 System Control Register 1 (SYSCR1) .................................................................84
6.1.2 System Control Register 2 (SYSCR2) .................................................................86
6.1.3 Module Standby Control Register 1 (MSTCR1)..................................................87
6.1.4 Module Standby Control Register 2 (MSTCR2)..................................................88
6.2 Mode Transitions and States of LSI ..................................................................................89
6.2.1 Sleep Mode ..........................................................................................................90
6.2.2 Standby Mode ......................................................................................................91
6.2.3 Subsleep Mode.....................................................................................................91
6.3 Operating Frequency in Active Mode ...............................................................................92
6.4 Direct Transition ...............................................................................................................92
6.5 Module Standby Function .................................................................................................92
Section 7 ROM ................................................................................................. 93
7.1 Block Configuration..........................................................................................................94
7.2 Register Descriptions ........................................................................................................96
7.2.1 Flash Memory Control Register 1 (FLMCR1).....................................................96
7.2.2 Flash Memory Control Register 2 (FLMCR2).....................................................97
7.2.3 Erase Block Register 1 (EBR1) ...........................................................................98
7.2.4 Flash Memory Enable Register (FENR) ..............................................................98
7.3 On-Board Programming Modes ........................................................................................99
7.3.1 Boot Mode ...........................................................................................................99
7.3.2 Programming/Erasing in User Program Mode.....................................................102
7.4 Flash Memory Programming/Erasing ...............................................................................103
7.4.1 Program/Program-Verify .....................................................................................103
7.4.2 Erase/Erase-Verify ...............................................................................................105
7.4.3 Interrupt Handling when Programming/Erasing Flash Memory..........................106
7.5 Program/Erase Protection..................................................................................................108
7.5.1 Hardware Protection ............................................................................................108
7.5.2 Software Protection..............................................................................................108
7.5.3 Error Protection....................................................................................................108
Section 8 RAM ................................................................................................. 109
Section 9 I/O Ports ............................................................................................ 111
9.1 Port 1.................................................................................................................................111
9.1.1 Port Mode Register 1 (PMR1) .............................................................................112
9.1.2 Port Control Register 1 (PCR1) ...........................................................................113
9.1.3 Port Data Register 1 (PDR1)................................................................................113
9.1.4 Port Pull-Up Control Register 1 (PUCR1)...........................................................114
9.1.5 Pin Functions .......................................................................................................114
Rev. 1.00, 11/03, page xi of xxviii
11 Page | ||
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