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76137SのメーカーはETCです、この部品の機能は「HUF76107D」です。 |
部品番号 | 76137S |
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部品説明 | HUF76107D | ||
メーカ | ETC | ||
ロゴ | |||
このページの下部にプレビューと76137Sダウンロード(pdfファイル)リンクがあります。 Total 11 pages
Data Sheet
HUF76107D3, HUF76107D3S
January 2003
20A, 30V, 0.052 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
These N-Channel power
MOSFETs are manufactured using
the innovative UltraFET™ process.
This advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is
capable of withstanding high energy in the avalanche mode
and the diode exhibits very low reverse recovery time and
stored charge. It was designed for use in applications
where power efficiency is important, such as switching
regulators, switching converters, motor drivers, relay
drivers, low voltage bus switches, and power management
in portable and battery operated products.
Formerly developmental type TA76107.
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF76107D3
TO-251AA
76107D
HUF76107D3S
TO-252AA
76107D
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF76107D3ST.
Packaging
JEDEC TO-251AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
Features
• Logic Level Gate Drive
• 20A, 30V
• Ultra Low On-Resistance, rDS(ON) = 0.052Ω
• Temperature Compensating PSPICE® Model
• Temperature Compensating SABER© Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-252AA
GATE
SOURCE
DRAIN
(FLANGE)
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
Free Datasheet http://www.datasheet4u.com/
1 Page HUF76107D3, HUF76107D3S
Electrical Specifications TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
tf
Turn-Off Time
tOFF
GATE CHARGE SPECIFICATIONS
VDD = 15V, ID ≅ 20A, RL =0.75Ω,
VGS = 10V, RGS = 33Ω
(Figures 16)
-
-
-
-
-
-
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Qg(TOT)
Qg(5)
Qg(TH)
Qgs
Qgd
VGS = 0V to 10V
VGS = 0V to 5V
VGS = 0V to 1V
VDD = 15V,ID ≅ 10.5A,
RL = 1.43Ω
Ig(REF) = 1.0mA
(Figure 14)
-
-
-
-
-
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
CISS
COSS
CRSS
VDS = 25V, VGS = 0V, f = 1MHz
(Figure 13)
-
-
-
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
VSD
trr
QRR
ISD = 10.5A
ISD = 10.5A, dISD/dt = 100A/µs
ISD = 10.5A, dISD/dt = 100A/µs
-
-
-
Typical Performance Curves Unless otherwise specified
TYP
-
18
30
62
20
-
8.6
4.7
0.35
1.00
2.40
315
170
30
TYP
-
-
-
MAX UNITS
75 ns
- ns
- ns
- ns
- ns
125 ns
10.3
5.7
0.42
-
-
nC
nC
nC
nC
nC
- pF
- pF
- pF
MAX
1.25
39
49
UNITS
V
ns
nC
1.2
1.0
0.8
0.6
0.4
0.2
0
0 25 50 75 100 125 150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
25
20
VGS = 10V
15
VGS = 4.5V
10
5
0
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
3Pages HUF76107D3, HUF76107D3S
Typical Performance Curves Unless otherwise specified (Continued)
600
VGS = 0V, f = 1MHz
500
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
400
CISS
300
200
100
0
0
COSS
CRSS
5 10 15 20 25
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
VDD = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
2 ID = 20A
ID = 12A
ID = 5A
0
0 2 4 6 8 10
Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
100
VGS = 4.5V, VDD = 15V, ID = 10A, RL= 1.50Ω
80
tr
60
td(OFF) tf
40
20
td(ON)
0
0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01Ω
100
VGS = 10V, VDD = 15V, ID = 20A, RL= 0.75Ω
80 td(OFF)
60 tr
tf
40
20 td(ON)
0
0 10
20 30 40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
©2003 Fairchild Semiconductor Corporation
HUF76107D3, HUF76107D3S Rev. B1
6 Page | |||
ページ | 合計 : 11 ページ | ||
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部品番号 | 部品説明 | メーカ |
76137S | HUF76107D | ETC |