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PDF MPC555PB Data sheet ( Hoja de datos )
| Número de pieza | MPC555PB | |
| Descripción | (MPC555) Microcontroller | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Product Brief
MPC555PB/D
Rev. 3, 2/2003
MPC555 Product Brief
This document provides an overview of the MPC555 microcontroller, including a block
diagram showing the major modular components and sections that list the major features. The
MPC555 member of the Motorola MPC500 RISC Microcontroller family.
Table 1. MPC555 Features
Device
MPC555
Flash
448 Kbytes
Code Compression
Code compression not supported
1 Introduction
The MPC555 device offers the following features:
• PowerPC™ core with floating-point unit
• 26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM
• 448 Kbytes Flash EEPROM with 5-V programming
• 5-V I/O system
• Serial system: queued serial multi-channel module (QSMCM), dual CAN 2.0B
controller
modules (TouCANTM)
• 50-channel timer system: dual time processor units (TPU3), modular I/O system
(MIOS1)
• 32 analog inputs: dual queued analog-to-digital converters (QADC64)
• Submicron HCMOS (CDR1) technology
• 272-pin plastic ball grid array (PBGA) packaging
• 40-MHz operation, -40 °C to 125 °C with dual supply (3.3 V, 5 V) (-55 °C to 125 °C
for the suffix A device)
• 32-bit architecture (PowerPC ISA architecture compliant)
• Core performance measured at 52.7-Kbyte Dhrystones (v2.1) @ 40 MHz
• Fully static, low power operation
• Integrated double-precision floating-point unit
• Precise exception model
1 page  
Key Features
1.2.10 Two CAN 2.0B Controller Modules (TouCAN)
Each TouCAN provides these features:
• Full implementation of CAN protocol specification, version 2.0A and 2.0B
• Each module has 16 receive/transmit message buffers of 0 to 8 bytes data length
• Global mask register for message buffers 0 to 13
• Independent mask registers for message buffers 14 and 15
• Programmable transmit-first scheme: lowest ID or lowest buffer number
• 16-bit free-running timer for message time-stamping
• Low power sleep mode with programmable wake-up on bus activity
• Programmable I/O modes
• Maskable interrupts
• Independent of the transmission medium (external transceiver is assumed)
• Open network architecture
• Multimaster concept
• High immunity to EMI
• Short latency time for high-priority messages
• Low power sleep mode with programmable wakeup on bus activity
1.2.11 Queued Serial Multi-Channel Module (QSMCM)
• Queued serial peripheral interface (QSPI)
— Provides full-duplex communication port for peripheral expansion or interprocessor
communication
— Up to 32 preprogrammed transfers, reducing overhead
— 160-byte queue buffer
— Programmable transfer length: from 8 to 16 bits, inclusive
— Synchronous interface with baud rate of up to system clock divided by 4
— Four programmable peripheral-select pins support up to 16 devices
— Wrap-around mode allows continuous sampling for efficient interfacing to serial peripherals
(e.g., – serial A/D converters, I/O latches, etc.)
• Two serial communications interfaces (SCI). Each SCI offers these features:
— UART mode provides NRZ format and half-or full-duplex interface
— 16 register receive buffer and 16 register transmit buffer (SCI1 only)
— Advanced error detection and optional parity generation and detection
— Word length programmable as 8 or 9 bits
— Separate transmitter and receiver enable bits and double buffering of data
— Wakeup functions allow the CPU to run uninterrupted until either a true idle line is detected or
a new address byte is received
— External source clock for baud generation
— Multiplexing of transmit data pins with discrete outputs and receive data pins with discrete
inputs, allowing realization of a low-speed serial protocol
MOTOROLA
MPC555 Product Brief
5
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Key Features
MOTOROLA
MPC555 Product Brief
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MPC555PB.PDF ] | |
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