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PDF ST92150 Data sheet ( Hoja de datos )
| Número de pieza | ST92150 | |
| Descripción | 8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM / E3 TMEMULATED EEPROM / CAN 2.0B AND J1850 BLPD | |
| Fabricantes | ST Microelectronics | |
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ST92F124/ST92F150/ST92F250
8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM,
E3 TM(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD
PRELIMINARY DATA
s Memories
– Internal Memory: Single Voltage FLASH up to 256
Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulat-
ed EEPROM)
– In-Application Programming (IAP)
– 224 general purpose registers (register file) availa-
ble as RAM, accumulators or index pointers
s Clock, Reset and Supply Management
– Register-oriented 8/16 bit CORE with RUN, WFI,
SLOW, HALT and STOP modes
– 0-24 MHz Operation (Int. Clock), 4.5-5.5 V range
– PLL Clock Generator (3-5 MHz crystal)
– Minimum instruction time: 83 ns (24 MHz int. clock)
s 80, 77 or 48 I/O pins (depending on device)
s Interrupt Management
– 80, 77 or 48 I/O pins (depending on device)
– 4 external fast interrupts + 1 NMI
– Up to 16 pins programmable as wake-up or addition-
al external interrupt with multi-level interrupt handler
– DMA controller for reduced processor overhead
s Timers
– 16-bit Timer with 8-bit Prescaler, and Watchdog Tim-
er (activated by software or by hardware)
– 16-bit Standard Timer that can be used to generate
a time base independent of PLL Clock Generator
– Two 16-bit independent Extended Function Timers
(EFTs) with Prescaler, 2 Input Captures and two
Output Compares (100-pin devices only)
– Two 16-bit Multifunction Timers, with Prescaler, 2 In-
put Captures and two Output Compares
s Communication Interfaces
– Serial Peripheral Interface (SPI) with Selectable
Master/Slave mode
TQFP64
14x14
PQFP100
14x20
TQFP100
14x14
– One Multiprotocol Serial Communications Interface
with asynchronous and synchronous capabilities
– One asynchronous Serial Communications Interface
(on 100-pin versions only) with 13-bit LIN Synch
Break generation capability
– J1850 Byte Level Protocol Decoder (JBLPD)
(on F150J versions only)
– One or two full I²C multiple Master/Slave Interfaces
supporting Access Bus
– One or two CAN 2.0B (150 version only) Active inter-
faces
s 10-bit Analog to Digital Converter allowing up to 16
input channels on 100-pin devices or 8 input channels
on 64-pin devices
s Development Tools
– Free High performance Development environment
(IDE) based on Visual Debugger, Assembler, Linker,
and C-Compiler; Real Time Operating System (OS-
EK OS, CMX) and CAN drivers
– Hardware Emulator and Flash Programming Board
for development and ISP Flasher for production
DEVICE SUMMARY
Features
ST92F124R9 ST92F124V1 ST92F150C(R/V)1
FLASH - bytes
64K
128K
128K
RAM - bytes
E3 TM - bytes
2K
1K
4K
1K
4K
1K
Timers and Serial
Interface
2 MFT, STIM,
WD, SCI, SPI,
I²C
2 MFT, 2 EFT,
STIM, WD,
2 SCI, SPI, I²C
2 MFT, 0/2 EFT,
STIM, WD,
1/2 SCI, SPI, I²C
ADC
8 x 10 bits
16 x 10 bits
8/16 x 10 bits
Network Interface
-
CAN
Temp. Range
-40°C to 85°C
-40°C to 105°C
-40°C to 105°C ,
-40°C to 125°C 2)
Packages
TQFP64
PQFP100
P/TQFP100 and
TQFP64
ST92F150JDV1
ST92F250CV2
128K
256K
6K 8K
1K 1K
2 MFT, 2 EFT, 2 MFT, 2 EFT, STIM,
STIM, WD,
2 SCI, SPI, I²C
WD, 2 SCI,
SPI, 2 I²C 1)
16 x 10 bits
2 CAN, J1850
CAN, LIN Master
-40o C to 125o C
-40°C to 105°C ,
-40°C to 125°C 2)
P/TQFP100
1) see Section 12.3 on page 396 for important information
2) see Table 70 on page 393
Rev. 1.3
December 2002
1/398
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 9
1 page  
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 1. ST92F124R9: Architectural Block Diagram
FLASH
64 Kbytes
E3 TM
1 Kbyte
RAM
2 Kbytes
NMI
INT[5:0]
WKUP[13:0]
OSCIN
OSCOUT
RESET
CLOCK2/8
INTCLK
CK_AF
STOUT
256 bytes
Register File
8/16 bits
CPU
Interrupt
Management
ST9 CORE
RCCU
ST. TIMER
TINPA0
TOUTA0
TINPB0
TOUTB0
TINPA1
TOUTA1
TINPB1
TOUTB1
MF TIMER 0
MF TIMER 1
VREG
VOLTAGE
REGULATOR
Fully
Prog.
I/Os
I2C BUS
WATCHDOG
SPI
ADC
SCI M
P0[7:0]
P1[2:0]
P2[7:0]
P3[7:4]
P4[7:4]
P5[7:0]
P6[5:2,0]
P7[7:0]
SDA
SCL
WDOUT
HW0SW1
MISO
MOSI
SCK
SS
AVDD
AVSS
AIN[15:8]
EXTRG
TXCLK
RXCLK
SIN
DCD
SOUT
CLKOUT
RTS
The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6
and Port7.
5/398
9
5 Page 
ST92F124/F150/F250 - GENERAL DESCRIPTION
1.2.3 Termination of Unused Pins
The ST9 device is implemented using CMOS tech-
nology; therefore unused pins must be properly
terminated in order to avoid application reliability
problems. In fact, as shown in Figure 6, the stand-
ard input circuitry is based on the CMOS inverter
structure.
Figure 6. CMOS basic inverter
VDD
OUT
P
N
IN
VSS
When an input is kept at logic zero, the N-channel
transistor is off, while the P-channel is on and can
conduct. The opposite occurs when an input is
kept at logic one. CMOS transistors are essentially
linear devices with relatively broad switching
points. During commutation, the input passes
through midsupply, and there is a region of input
voltage values where both P and N-channel tran-
sistors are on. Since normally the transitions are
fast, there is a very short time in which a current
can flow: once the switching is completed there is
no longer current. This phenomenon explains why
the overall current depends on the switching rate:
the consumption is directly proportional to the
number of transistors inside the device which are
in the linear region during transitions, charging and
discharging internal capacitances.
In order to avoid extra power supply current, it is
important to bias input pins properly when not
used. In fact, if the input impedance is very high,
pins can float, when not connected, either to a
midsupply level or can oscillate (injecting noise in
the device).
Depending on the specific configuration of each
I/O pin on different ST9 devices, it can be more or
less critical to leave unused pins floating. For this
reason, on most pins, the configuration after RE-
SET enables an internal weak pull-up transistor in
order to avoid floating conditions. For other pins
this is intrinsically forbidden, like for the true open-
drain pins. In any case, the application software
must program the right state for unused pins to
avoid conflicts with external circuitry (whichever it
is: pull-up, pull-down, floating, etc.).
The suggested method of terminating unused I/O
is to connect an external individual pull-up or pull-
down for each pin, even though initialization soft-
ware can force outputs to a specified and defined
value, during a particular phase of the RESET rou-
tine there could be an undetermined status at the
input section.
Usage of pull-ups and/or pull-downs is preferable
in place of direct connection to VDD or VSS. If pull-
up or pull-down resistors are used, inputs can be
forced for test purposes to a different value, and
outputs can be programmed to both digital levels
without generating high current drain due to the
conflict.
Anyway, during system verification flow, attention
must be paid to reviewing the connection of each
pin, in order to avoid potential problems.
1.2.4 Avoidance of Pin Damage
Although integrated circuit data sheets provide the
user with conservative limits and conditions in or-
der to prevent damage, sometimes it is useful for
the hardware system designer to know the internal
failure mechanisms: the risk of exposure to illegal
voltages and conditions can be reduced by smart
protection design.
It is not possible to classify and to predict all the
possible damage resulting from violating maxi-
mum ratings and conditions, due to the large
number of variables that come into play in defining
the failures: in fact, when an overvoltage condition
is applied, the effects on the device can vary sig-
nificantly depending on lot-to-lot process varia-
tions, operating temperature, external interfacing
of the ST9 with other devices, etc.
In the following sections, background technical in-
formation is given in order to help system design-
ers to reduce risk of damage to the ST9 device.
1.2.4.1 Electrostatic Discharge and Latchup
CMOS integrated circuits are generally sensitive
to exposure to high voltage static electricity, which
can induce permanent damage to the device: a
typical failure is the breakdown of thin oxides,
which causes high leakage current and sometimes
shorts.
Latchup is another typical phenomenon occurring
in integrated circuits: unwanted turning on of para-
sitic bipolar structures, or silicon-controlled rectifi-
11/398
9
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| PDF Descargar | [ Datasheet ST92150.PDF ] | |
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