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ID82C52 の電気的特性と機能

ID82C52のメーカーはIntersil Corporationです、この部品の機能は「CMOS Serial Controller Interface」です。


製品の詳細 ( Datasheet PDF )

部品番号 ID82C52
部品説明 CMOS Serial Controller Interface
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ID82C52 Datasheet, ID82C52 PDF,ピン配置, 機能
82C52
March 1997
CMOS Serial Controller Interface
Features
• Single Chip UART/BRG
• DC to 16MHz (1M Baud) Operation
• Crystal or External Clock Input
• On-Chip Baud Rate Generator - 72 Selectable Baud
Rates
• Interrupt Mode with Mask Capability
• Microprocessor Bus Oriented Interface
• 80C86 Compatible
• Single +5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . 1mA/MHz Typ
• Modem Interface
• Line Break Generation and Detection
• Operating Temperature Range:
- C82C52 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C52 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C52 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Description
The Intersil 82C52 is a high performance programmable
Universal Asynchronous Receiver/Transmitter (UART) and
Baud Rate Generator (BRG) on a single chip. Utilizing the
Intersil advanced Scaled SAJI IV CMOS process, the 82C52
will support data rates up to 1M baud asynchronously with a
16X clock (16MHz clock frequency).
The on-chip Baud Rate Generator can be programmed for
any one of 72 different baud rates using a single industry
standard crystal or external frequency source. A unique pre-
scale divide circuit has been designed to provide standard
RS-232-C baud rates when using any one of three industry
standard crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).
A programmable buffered clock output (CO) is available and
can be programmed to provide either a buffered oscillator or
16X baud rate clock for general purpose system usage.
Ordering Information
PACKAGE
PDIP
PLCC
CERDIP
SMD#
CLCC
SMD#
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
1M BAUD
CP82C52
IP82C52
CS82C52
IS82C52
CD82C52
ID82C52
MD82C52/B
8501501XA
MR82C52/B
85015013A
PKG. NO.
E28.6
E28.6
N28.45
N28.45
F28.6
F28.6
F28.6
F28.6
J28.A
J28.A
Pinouts
82C52 (PDIP, CERDIP)
TOP VIEW
RD 1
WR 2
D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
A0 11
A1 12
IX 13
OX 14
28 CSO
27 VCC
26 DR
25 SDI
24 INTR
23 RST
22 TBRE
21 CO
20 RTS
19 DTR
18 DSR
17 CTS
16 GND
15 SDO
82C52 (PLCC, CLCC)
TOP VIEW
4 3 2 1 28 27 26
D2 5
25 SDI
D3 6
24 INTR
D4 7
23 RST
D5 8
D6 9
22 TBRE
21 CO
D7 10
20 RTS
A0 11
19 DTR
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-1
File Number 2950.1

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ID82C52 pdf, ピン配列
82C52
Pin Description (Continued)
PIN ACTIVE
SYMBOL NO. TYPE LEVEL
DESCRIPTION
DSR 18 I
Low DATA SET READY: The logical state of the DSR line is reflected in the Modem Status Register.
Any change of state of DSR will cause INTR to be set if INTEN and MIEN are true. The state
of this signal does not affect any other circuitry within the 82C52.
DTR
19 O
Low DATA TERMINAL READY: The DTR signal can be set (low) by writing a logic 1 to the appro-
priate bit in the Modem Control Register (MCR). This signal is cleared (high) by writing a logic
0 in the DTR bit in the MCR or whenever a reset (RST = high) is applied to the 82C52.
RTS 20 O Low REQUEST TO SEND: The RTS signal can be set (low) by writing a logic 1 to the appropriate
bit in the MCR. This signal is cleared (high) by writing a logic 0 to the RTS bit in the MCR or
whenever a reset (RST = high) is applied to the 82C52.
CO 21 O
CLOCK OUT: This output is user programmable to provide either a buffered IX output or a
buffered Baud Rate Generator (16X) clock output. The buffered IX (Crystal or external clock
source) output is provided when the Baud Rate Select Register (BRSR) bit 7 is set to a zero.
Writing a logic one to BRSR bit 7 causes the CO output to provide a buffered version of the
internal Baud Rate Generator clock which operates at sixteen times the programmed baud
rate. On reset D7 (CO select) is reset to 0.
TBRE 22 O High TRANSMITTER BUFFER REGISTER EMPTY: The TBRE output is set (high) whenever the
Transmitter Buffer Register (TBR) has transferred its data to the Transmit Register. Application
of a reset (RST) to the 82C52 will also set the TBRE output. TBRE is cleared (low) whenever
data is written to the TBR.
RST 23 I High RESET: The RST input forces the 82C52 into an “Idle” mode in which all serial data activities
are suspended. The Modem Control Register (MCR) along with its associated outputs are
cleared. The UART Status Register (USR) is cleared except for the TBRE and TC bits, which
are set. The 82C52 remains in an “Idle” state until programmed to resume serial data activities.
The RST input is a Schmitt triggered input.
INTR
24 O
High
INTERRUPT REQUEST: The INTR output is enabled by the INTEN bit in the Modem Control
Register (MCR). The MIEN bit selectively enables modem status changes to provide an input
to the INTR logic. Figure 9 in Design Information shows the overall relationship of these inter-
rupt control signals.
SDI 25 I High SERIAL DATA INPUT: Serial data input to the 82C52 receiver circuits. A Mark (1) is high, and
a Space (0) is low. Data inputs on SDI are disabled when operating in the loop mode or when
RST is true.
DR 26 O High DATA READY: A true level indicates that a character has been received, transferred to the
RBR, and is ready for transfer to the CPU. DR is reset on a data READ of the Receiver Buffer
Register (RBR) or when RST is true.
VCC
27
High
VCC: +5V positive power supply pin. A 0.1µF decoupling capacitor from VCC (Pin 27) to GND
(Pin 16) is recommended.
CS0 28 I Low CHIP SELECT: The chip select input acts as an enable signal for the RD and WR input
signals.
5-3


3Pages


ID82C52 電子部品, 半導体
82C52
disabled from the SDO output pin. The Receiver Enable bit
gates off the input to the receiver circuitry when in the false
state.
Modem Interrupt Enable will permit any change in modem
status line inputs (CTS, DSR) to cause an interrupt when
this bit is enabled. Bit D7 must always be written to with a
logic zero to insure correct 82C52 operation.
D7 D6 D5 D4 D3 D2 D1 D0
Request 0 = RTS Output High
to Send 1 = RTS Output Low
(RTS)
Data
Terminal
Ready
(DTR)
0 = DTR Output High
1 = DTR Output Low
Interrupt 1 = Interrupts Enabled
Enable 0 = interrupts Disabled
(INTEN)
Mode
Select
00 = Normal
01 = Transmit Break
10 = Echo Mode
11 = Loop Test Mode
Receiver 0 = Not Enabled
Enable 1 = Enabled
(REN)
Modem
Interrupt
Enable
(MIEN)
0 = Not Enabled
1 = Enabled
Must be Set to a Logic 0 for
Normal 82C52 Operation
See Modem Status Register description for a description of
register flag images with respect to output pins.
FIGURE 3. MCR
Three error flags OE, FE and PE report the status of any
error conditions detected in the receiver circuitry. These
error flags are updated with every character received during
reception of the stop bits. The Overrun Error (OE) indicates
that a character in the Receiver Register has been received
and cannot be transferred to the Receiver Buffer Register
(RBR) because the RBR was not read by the CPU. Framing
Error (FE) indicates that the last character received in the
RBR contained improper stop bits. This could be caused by
the absence of the required stop bit(s) or by a stop bit(s) that
was too short to be properly detected. Parity Error (PE) indi-
cates that the last character received in the RBR contained a
parity error based on the programmed parity of the receiver
and the calculated parity of the received character data and
parity bits.
The Received Break (RBRK) status bit indicates that the last
character received was a break character. A break character
would be considered to be an invalid data character in that
the entire character including parity and stop bits are a logic
zero.
The Modem Status bit is set whenever a transition is
detected on any of the Modem input lines (CTS or DSR). A
subsequent read of the Modem Status Register will show the
state of these two signals. Assertion of this bit will cause an
interrupt (INTR) to be generated if the MIEN and INTEN bits
in the MCR register are enabled.
The Transmission Complete (TC) bit indicates that both the
TBR and Transmitter Registers are empty and the 82C52
has completed transmission of the last character it was com-
manded to transmit. The assertion of this bit will cause an
interrupt (INTR) if the INTEN bit in the MCR register is true.
The Transmitter Buffer Register Empty (TBRE) bit indicates
that the TBR register is empty and ready to receive another
character.
SERIAL DATA
FROM
TRANSMITTER
REGISTER
ECHO MODE
SERIAL DATA
TO RECEIVER
REGISTER
LOOP
MODE
SDO
PIN 15
SDI
PIN 25
The Data Ready (DR) bit indicates that the RBR has been
loaded with a received character (including Break) and that
the CPU may access this data.
Assertion of the TBRE or DR bits do not affect the INTR
logic and associated INTR output pin since the 82C52 has
been designed to provide separate requests via the DR and
TBRE output pins. If a single interrupt for any status change
in the 82C52 is desired this can be accomplished by using
an 82C59A Interrupt controller with DR, TBRE, and INTR as
inputs. (See Figure 11).
FIGURE 4. LOOP AND ECHO MODE FUNCTIONALITY
UART Status Register (USR)
The USR provides a single register that the controlling sys
tem can examine to determine if errors have occurred or if
other status changes in the 82C52 require attention. For this
reason, the USR is usually the first register read by the CPU
to determine the cause of an interrupt or to poll the status of
the 82C52.
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共有リンク

Link :


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