DataSheet.jp

ID82C54 の電気的特性と機能

ID82C54のメーカーはIntersil Corporationです、この部品の機能は「CMOS Programmable Interval Timer」です。


製品の詳細 ( Datasheet PDF )

部品番号 ID82C54
部品説明 CMOS Programmable Interval Timer
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




このページの下部にプレビューとID82C54ダウンロード(pdfファイル)リンクがあります。

Total 17 pages

No Preview Available !

ID82C54 Datasheet, ID82C54 PDF,ピン配置, 機能
82C54
March 1997
CMOS Programmable Interval Timer
Features
Description
• 8MHz to 12MHz Clock Input Frequency
• Compatible with NMOS 8254
- Enhanced Version of NMOS 8253
• Three Independent 16-Bit Counters
• Six Programmable Counter Modes
• Status Read Back Command
• Binary or BCD Counting
• Fully TTL Compatible
• Single 5V Power Supply
• Low Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA at 8MHz
• Operating Temperature Ranges
- C82C54 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C54 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C54 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C54 is a high performance CMOS Program-
mable Interval Timer manufactured using an advanced 2
micron CMOS process.
The 82C54 has three independently programmable and
functional 16-bit counters, each capable of handling clock
input frequencies of up to 8MHz (82C54) or 10MHz
(82C54-10) or 12MHz (82C54-12).
The high speed and industry standard configuration of the
82C54 make it compatible with the Intersil 80C86, 80C88,
and 80C286 CMOS microprocessors along with many other
industry standard processors. Six programmable timer
modes allow the 82C54 to be used as an event counter,
elapsed time indicator, programmable one-shot, and many
other applications. Static CMOS circuit design insures low
power operation.
The Intersil advanced CMOS process results in a significant
reduction in power with performance equal to or greater than
existing equivalent products.
Pinouts
82C54 (PDIP, CERDIP, SOIC)
TOP VIEW
D7 1
D6 2
D5 3
D4 4
D3 5
D2 6
D1 7
D0 8
CLK 0 9
OUT 0 10
GATE 0 11
GND 12
24 VCC
23 WR
22 RD
21 CS
20 A1
19 A0
18 CLK 2
17 OUT 2
16 GATE 2
15 CLK 1
14 GATE 1
13 OUT 1
82C54 (PLCC/CLCC)
TOP VIEW
4 3 2 1 28 27 26
D4 5
D3 6
D2 7
D1 8
D0 9
CLK 0 10
NC 11
25 NC
24 CS
23 A1
22 A0
21 CLK2
20 OUT 2
19 GATE 2
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-1
File Number 2970.1

1 Page





ID82C54 pdf, ピン配列
82C54
Pin Description (Continued)
SYMBOL
CLK 2
A0, A1
DIP PIN
NUMBER
18
19 - 20
TYPE
I
I
DEFINITION
CLOCK 2: Clock input of Counter 2.
ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write
operations. Normally connected to the system address bus.
A1 A0
SELECTS
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
CS
RD
WR
VCC
21
22
23
24
I CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and
WR are ignored otherwise.
I READ: This input is low during CPU read operations.
I WRITE: This input is low during CPU write operations.
VCC: The +5V power supply pin. A 0.1µF capacitor between pins VCC and GND is recommended
for decoupling.
Functional Description
General
The 82C54 is a programmable interval timer/counter
designed for use with microcomputer systems. It is a general
purpose, multi-timing element that can be treated as an
array of I/O ports in the system software.
D7 - D0
8
DATA/
BUS
BUFFER
COUNTER
0
CLK 0
GATE 0
OUT 0
The 82C54 solves one of the most common problems in any
microcomputer system, the generation of accurate time
delays under software control. Instead of setting up timing
loops in software, the programmer configures the 82C54 to
match his requirements and programs one of the counters
for the desired delay. After the desired delay, the 82C54 will
interrupt the CPU. Software overhead is minimal and vari-
able length delays can easily be accommodated.
Some of the other computer/timer functions common to micro-
computers which can be implemented with the 82C54 are:
• Real time clock
• Event counter
• Digital one-shot
• Programmable rate generator
• Square wave generator
• Binary rate multiplier
• Complex waveform generator
• Complex motor controller
Data Bus Buffer
This three-state, bi-directional, 8-bit buffer is used to inter-
face the 82C54 to the system bus (see Figure 1).
RD
WR
READ/
WRITE
A0 LOGIC
A1
CS
CONTROL
WORD
REGISTER
COUNTER
1
CLK 1
GATE 1
OUT 1
COUNTER
2
CLK 2
GATE 2
OUT 2
FIGURE 1. DATA BUS BUFFER AND READ/WRITE LOGIC
FUNCTIONS
Read/Write Logic
The Read/Write Logic accepts inputs from the system bus and
generates control signals for the other functional blocks of the
82C54. A1 and A0 select one of the three counters or the Con-
trol Word Register to be read from/written into. A “low” on the
RD input tells the 82C54 that the CPU is reading one of the
counters. A “low” on the WR input tells the 82C54 that the CPU
is writing either a Control Word or an initial count. Both RD and
WR are qualified by CS; RD and WR are ignored unless the
82C54 has been selected by holding CS low.
4-3


3Pages


ID82C54 電子部品, 半導体
82C54
Possible Programming Sequence (Continued)
LSB of Count - Counter 1
LSB of Count - Counter 0
MSB of Count - Counter 0
MSB of Count - Counter 1
MSB of Count - Counter 2
A1
0
0
0
0
1
A0
1
0
0
1
0
Possible Programming Sequence
Control Word - Counter 2
Control Word - Counter 1
Control Word - Counter 0
LSB of Count - Counter 2
MSB of Count - Counter 2
LSB of Count - Counter 1
MSB of Count - Counter 1
LSB of Count - Counter 0
MSB of Count - Counter 0
A1 A0
11
11
11
10
10
01
01
00
00
Possible Programming Sequence
A1 A0
Control Word - Counter 1
11
Control Word - Counter 0
11
LSB of Count - Counter 1
01
Control Word - Counter 2
11
LSB of Count - Counter 0
00
MSB of Count - Counter 1
01
LSB of Count - Counter 2
10
MSB of Count - Counter 0
00
MSB of Count - Counter 2
10
NOTE: In all four examples, all counters are programmed to
Read/Write two-byte counts. These are only four of many
programming sequences.
A new initial count may be written to a Counter at any time
without affecting the Counter’s programmed Mode in any way.
Counting will be affected as described in the Mode definitions.
The new count must follow the programmed count format.
If a Counter is programmed to read/write two-byte counts,
the following precaution applies. A program must not transfer
control between writing the first and second byte to another
routine which also writes into that same Counter. Otherwise,
the Counter will be loaded with an incorrect count.
Read Operations
It is often desirable to read the value of a Counter without
disturbing the count in progress. This is easily done in the
82C54.
There are three possible methods for reading the Counters.
The first is through the Read-Back command, which is
explained later. The second is a simple read operation of the
Counter, which is selected with the A1, A0 inputs. The only
requirement is that the CLK input of the selected Counter
must be inhibited by using either the GATE input or external
logic. Otherwise, the count may be in process of changing
when it is read, giving an undefined result.
Counter Latch Command
The other method for reading the Counters involves a spe-
cial software command called the “Counter Latch Com-
mand”. Like a Control Word, this command is written to the
Control Word Register, which is selected when A1, A0 = 11.
Also, like a Control Word, the SC0, SC1 bits select one of
the three Counters, but two other bits, D5 and D4, distin-
guish this command from a Control Word.
.
A1, A0 = 11; CS = 0; RD = 1; WR = 0
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 0 0 X X X X
SC1, SC0 - specify counter to be latched
SC1 SC0
COUNTER
00
0
01
1
10
2
11
Read-Back Command
D5, D4 - 00 designates Counter Latch Command, X - Don’t Care.
NOTE: Don’t Care bits (X) should be 0 to insure compatibility with
future products.
The selected Counter’s output latch (OL) latches the count
when the Counter Latch Command is received. This count is
held in the latch until it is read by the CPU (or until the Counter
is reprogrammed). The count is then unlatched automatically
and the OL returns to “following” the counting element (CE).
This allows reading the contents of the Counters “on the fly”
without affecting counting in progress. Multiple Counter Latch
Commands may be used to latch more than one Counter.
Each latched Counter’s OL holds its count until read. Counter
Latch Commands do not affect the programmed Mode of the
Counter in any way.
If a Counter is latched and then, some time later, latched
again before the count is read, the second Counter Latch
Command is ignored. The count read will be the count at the
time the first Counter Latch Command was issued.
With either method, the count must be read according to the
programmed format; specifically, if the Counter is pro-
grammed for two byte counts, two bytes must be read. The
two bytes do not have to be read one right after the other;
read or write or programming operations of other Counters
may be inserted between them.
Another feature of the 82C54 is that reads and writes of the
same Counter may be interleaved; for example, if the
Counter is programmed for two byte counts, the following
sequence is valid.
4-6

6 Page



ページ 合計 : 17 ページ
 
PDF
ダウンロード
[ ID82C54 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
ID82C50A

CMOS Asynchronous Communications Element

Intersil Corporation
Intersil Corporation
ID82C52

CMOS Serial Controller Interface

Intersil Corporation
Intersil Corporation
ID82C54

CMOS Programmable Interval Timer

Intersil Corporation
Intersil Corporation
ID82C55A

CMOS Programmable Peripheral Interface

Harris Corporation
Harris Corporation


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap