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PDF INT5130 Data sheet ( Hoja de datos )
| Número de pieza | INT5130 | |
| Descripción | Integrated Powerline MAC/PHY Transceiver | |
| Fabricantes | Intellon | |
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TECHNICAL DATA SHEET
INT5130
Integrated Powerline
MAC/PHY Transceiver
Features
§ Single-chip powerline networking controller with
IEEE802.3u MII interface
§ Implements Intellon’s PowerPacket™ technology which
is fully compliant with the HomePlug Powerline Alliance
Industry Specification v1.0
§ General purpose 8-wire serial PHY data interface
§ Selectable MDI/SPI PHY management interface
§ Up to 14 Mbps data rate on the powerline
§ Orthogonal Frequency Division Multiplexing (OFDM) with
patented signal processing techniques for high data
reliability in noisy media conditions
§ Intelligent channel adaptation maximizes throughput
under harsh channel conditions
§ Integrated quality-of-service (QoS) features such as
prioritized random access, contention-free access, and
segment bursting
§ 56-bit DES Link Encryption with key management for
secure powerline communications
§ E2PROM interface for fast access to configuration
parameters allows system designs to leverage standard
Ethernet drivers
§ IEEE 1149.1 JTAG Test Access Port
§ 3.3 V signaling, 5 V tolerant interface
§ Support for three status LEDs
§ 144-pin LQFP package
Applications
§ Shared broadband Internet access
using standard in-home powerlines
§ Internet Appliances
§ PC file and application sharing
§ Peripheral and printer sharing
§ Networked gaming
General Description
The INT5130 IC is an integrated powerline MAC/PHY transceiver providing No New WiresTM communications
to any room, over any wire, at speeds of up to 14 Mbps. The INT5130 provides the ability to select between a
complete Media Independent Interface (MII) or a reduced General Purpose Serial Interface (GPSI) for
interconnection to the external MAC controller. The INT5130 also provides the option of selecting between a
Management Data Interface (MDI) or a simple Serial Peripheral Interface (SPI) for handling the management
and control of the MII/GPSI interface.
INTELLON CONFIDENTIAL
Rev 8.1
1 ADVANCE INFORMATION
1 page  
INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Pin Descriptions by Group
Signal Name
I/O Pad Description
Signal Description
Media Independent Interface (MII)
These pins are multiplexed with the GPSI pins and are selected when MII_GSPI_N signal is at VDD.
MII_RX[3:0]
Output
MII Receive Data.
Data is transferred from the INT5130 to the external
MAC across these four lines one nibble at a time.
MII_RXCLK
Output
MII Receive Clock
The receive clock outputs a continuous 25MHz clock
to the external MAC.
MII_RXDV
Output
MII Receive Data Valid
This signal indicates that the incoming data on the
MII_RX[3:0] pins are valid.
MII_RX_ER
Output
MII Receive Error
This signal indicates to the external MAC that an
error has occurred during the frame reception.
MII_TX[3:0]
Input
MII Transmit Data
Data is transferred to the INT5130 from the external
MAC across these four lines one nibble at a time.
MII_TXCLK
Output
MII Transmit Clock
The transmit clock outputs a continuous 25MHz
clock to the external MAC.
MII_TXEN
Input
MII Transmit Enable
This signal indicates to the INT5130 that valid data
is present on the MII_TX[3:0] pins.
MII_TX_ER
Input
MII Transmit Error
MII_TX_ER is activated by the external host
controller when an error condition is detected during
packet transmission. The INT5130 will ignore any
MII transmission within which MII_TX_ER is
asserted. MII_TX_ER is ignored if MII_TXEN is not
asserted.
MII_CRS
Output
MII Carrier Sense
This signal indicates to the external host that traffic
is present on the powerline and the host should wait
until the signal goes invalid before sending additional
data. This signal is an asynchronous output signal.
MII_COL
Output
MII Collision Detect
This signal indicates to the external host that a
collision has occurred on the MII interface. This
signal is an asynchronous output signal.
MII Management Data Interface (MDI)
These pins are multiplexed with the SPIS_SDO and SPIS_SCLK signals and are selected when MDI_SPIS_N is at VDD.
MII_MDIO
Input/Output
MII Management Data Input/Output
This bi-directional signal carries the data for the
Management Data Interface.
MII_MDCLK
Input
MII Management Data Clock
Clock reference for the MII_MDIO signal.
INTELLON CONFIDENTIAL
Rev 8.1
5
ADVANCE INFORMATION
5 Page 
INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
MII Data Interface with MDI Control
Data communication between the INT5130 and the external host controller is provided via the Media
Independent Interface or a reduced General Purpose Serial Interface. The MII_GPSI_N select pin is included
on the chip interface to configure the INT5130 in either MII mode or GPSI mode. Access to the INT5130’s
internal MII status and control registers is via the Management Data Interface or a SPI interface. The
MDI_SPIS_N select pin is included on the chip interface to configure the INT5130 in either MDI mode or SPI
mode. The information that follows describes the MII communication interface along with the MDI management
interface as a typical example.
External
Host
Controller
MII_RX(3:0)
MII_RXCLK
MII_RX_ER
MII_RXDV
MII_CRS
MII_COL
MII_TX(3:0)
MII_TXCLK
MII_TX_ER
MII_TXEN
MII_MDCLK
MII_MDIO
INT5130
Figure 2: MII Data Interface with MDI Control
MII Interface
MII is an industry standard, multi-vendor, interoperable interface between separate MAC and PHY devices.
It provides a simple interconnection between the INT5130 and IEEE802.3 Ethernet MAC controllers
(commonly referred to as external host controllers in this document) available from a variety of IC suppliers.
The MII consists of separate 4-bit data paths for transmit and receive data along with carrier sense and
collision detection. Data is transferred between the MAC and PHY over each 4-bit data path synchronous
with a clock signal supplied to the host by the INT5130. The MII interface also provides a two wire bi-
directional serial management data interface (MDI). This interface provides access to the status and
control registers in the INT5130.
MII Timing Diagrams
Figure 3 below shows the transmission behavior of the MII interface. Figure 4 shows the receive
behavior of the MII interface. Figure 5 shows an unsuccessful attempt to transmit a packet, resulting in
a collision.
NOTE: MII_CRS is asynchronous to MII_TXCLK.
INTELLON CONFIDENTIAL
Rev 8.1
11
ADVANCE INFORMATION
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet INT5130.PDF ] | |
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