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UPD4481362 の電気的特性と機能

UPD4481362のメーカーはNECです、この部品の機能は「(UPD4481162/1182/1322/1362) 8M-BIT ZEROSB SRAM PIPELINED OPERATION」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD4481362
部品説明 (UPD4481162/1182/1322/1362) 8M-BIT ZEROSB SRAM PIPELINED OPERATION
メーカ NEC
ロゴ NEC ロゴ 




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UPD4481362 Datasheet, UPD4481362 PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4481162, 4481182, 4481322, 4481362
8M-BIT ZEROSBTM SRAM
PIPELINED OPERATION
Description
The µPD4481162 is a 524,288-word by 16-bit, the µPD4481182 is a 524,288-word by 18-bit, the µPD4481322 is a
262,144-word by 32-bit and the µPD4481362 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with
advanced CMOS technology using full CMOS six-transistor memory cell.
The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are optimized to eliminate dead cycles for read to
write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the
single clock input (CLK).
The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are suitable for applications which require
synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).
In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal
operation.
The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are packaged in 100-pin PLASTIC LQFP with a 1.4
mm package thickness for high density and low capacitive loading.
Features
Low voltage core supply : VDD = 3.3 ± 0.165 V (-A44, -A50, -A60, -A75, -A44Y, -A50Y, -A60Y, -A75Y)
VDD = 2.5 ± 0.125 V (-C60, -C75, -C60Y, -C75Y)
Synchronous operation
Operating temperature : TA = 0 to 70 °C (-A44, -A50, -A60, -A75, -C60, -C75)
TA = 40 to +85 °C (-A44Y, -A50Y, -A60Y, -A75Y, -C60Y, -C75Y)
100 percent bus utilization
Internally self-timed write control
Burst read / write : Interleaved burst and linear burst sequence
Fully registered inputs and outputs for pipelined operation
All registers triggered off positive clock edge
3.3V or 2.5V LVTTL Compatible : All inputs and outputs
Fast clock access time : 2.8 ns (225 MHz), 3.2 ns (200 MHz), 3.5 ns (167 MHz) , 4.2 ns (133 MHz)
Asynchronous output enable : /G
Burst sequence selectable : MODE
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
Separate byte write enable : /BW1 to /BW4 (µPD4481322 and µPD4481362)
/BW1 and /BW2 (µPD4481162 and µPD4481182)
Three chip enables for easy depth expansion
Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15562EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan
The mark  shows major revised points.
2001

1 Page





UPD4481362 pdf, ピン配列
µPD4481162, 4481182, 4481322, 4481362
Part number
µPD4481162GF-A44Y
µPD4481162GF-A50Y
µPD4481162GF-A60Y
µPD4481162GF-A75Y
µPD4481182GF-A44Y
µPD4481182GF-A50Y
µPD4481182GF-A60Y
µPD4481182GF-A75Y
µPD4481322GF-A44Y
µPD4481322GF-A50Y
µPD4481322GF-A60Y
µPD4481322GF-A75Y
µPD4481362GF-A44Y
µPD4481362GF-A50Y
µPD4481362GF-A60Y
µPD4481362GF-A75Y
µPD4481162GF-C60Y
µPD4481162GF-C75Y
µPD4481182GF-C60Y
µPD4481182GF-C75Y
µPD4481322GF-C60Y
µPD4481322GF-C75Y
µPD4481362GF-C60Y
µPD4481362GF-C75Y
Access
Time
ns
2.8
3.2
3.5
4.2
2.8
3.2
3.5
4.2
2.8
3.2
3.5
4.2
2.8
3.2
3.5
4.2
3.5
4.2
3.5
4.2
3.5
4.2
3.5
4.2
Clock
Frequency
MHz
225
200
167
133
225
200
167
133
225
200
167
133
225
200
167
133
167
133
167
133
167
133
167
133
Core Supply
Voltage
V
3.3 ± 0.165
2.5 ± 0.125
I/O Interface
3.3 V LVTTL Note
3.3 V or 2.5 V LVTTL
(2/2)
Operating
Package
Temperature
°C
40 to +85 100-pin PLASTIC
LQFP (14 x 20)
3.3 V LVTTL Note
3.3 V or 2.5 V LVTTL
3.3 V LVTTL Note
3.3 V or 2.5 V LVTTL
3.3 V LVTTL Note
3.3 V or 2.5 V LVTTL
2.5 V LVTTL
Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A60Y (167 MHz).
Data Sheet M15562EJ3V0DS
3


3Pages


UPD4481362 電子部品, 半導体
µPD4481162, 4481182, 4481322, 4481362
100-pin PLASTIC LQFP (14 × 20)
[µPD4481322GF, µPD4481362GF]
Marking Side
I/OP3, NC
I/O17
I/O18
VDDQ
VSSQ
I/O19
I/O20
I/O21
I/O22
VSSQ
VDDQ
I/O23
I/O24
VDD
VDD
VDD
VSS
I/O25
I/O26
VDDQ
VSSQ
I/O27
I/O28
I/O29
I/O30
VSSQ
VDDQ
I/O31
I/O32
I/OP4, NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
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30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/OP2, NC
I/O16
I/O15
VDDQ
VSSQ
I/O14
I/O13
I/O12
I/O11
VSSQ
VDDQ
I/O10
I/O9
VSS
VDD
VDD
ZZ
I/O8
I/O7
VDDQ
VSSQ
I/O6
I/O5
I/O4
I/O3
VSSQ
VDDQ
I/O2
I/O1
I/OP1, NC
Remark Refer to Package Drawing for the 1-pin index mark.
6 Data Sheet M15562EJ3V0DS

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
UPD4481361

(UPD4481161/1181/1321/1361) 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION

NEC
NEC
UPD4481362

(UPD4481162/1182/1322/1362) 8M-BIT ZEROSB SRAM PIPELINED OPERATION

NEC
NEC


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