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UPD4482362 の電気的特性と機能

UPD4482362のメーカーはNECです、この部品の機能は「(UPD4482162/2182/2322/2362) 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD4482362
部品説明 (UPD4482162/2182/2322/2362) 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT
メーカ NEC
ロゴ NEC ロゴ 




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UPD4482362 Datasheet, UPD4482362 PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4482162, 4482182, 4482322, 4482362
8M-BIT CMOS SYNCHRONOUS FAST SRAM
PIPELINED OPERATION
SINGLE CYCLE DESELECT
Description
The µPD4482162 is a 524,288-word by 16-bit, the µPD4482182 is a 524,288-word by 18-bit, µPD4482322 is a 262,144-
word by 32-bit and the µPD4482362 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS
technology using Full-CMOS six-transistor memory cell.
The µPD4482162, µPD4482182, µPD4482322 and µPD4482362 integrates unique synchronous peripheral circuitry, 2-
bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single
clock input (CLK).
The µPD4482162, µPD4482182, µPD4482322 and µPD4482362 are suitable for applications which require synchronous
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In
the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The µPD4482162, µPD4482182, µPD4482322 and µPD4482362 are packaged in 100-pin PLASTIC LQFP with a 1.4
mm package thickness for high density and low capacitive loading.
Features
3.3 V or 2.5 V core supply
Synchronous operation
Operating temperature : TA = 0 to 70 °C (-A44, -A50, -A60, -C60)
TA = 40 to +85 °C (-A44Y, -A50Y, -A60Y, -C60Y)
Internally self-timed write control
Burst read / write : Interleaved burst and linear burst sequence
Fully registered inputs and outputs for pipelined operation
Single-Cycle deselect timing
All registers triggered off positive clock edge
3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs
Fast clock access time : 2.8 ns (225 MHz), 3.1 ns (200 MHz), 3.5 ns (167 MHz)
Asynchronous output enable : /G
Burst sequence selectable : MODE
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
Separate byte write enable : /BW1 to /BW4, /BWE (µPD4482322, µPD4482362)
/BW1, /BW2, /BWE (µPD4482162, µPD4482182)
Global write enable : /GW
Three chip enables for easy depth expansion
Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M14522EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan
The mark  shows major revised points.
2000

1 Page





UPD4482362 pdf, ピン配列
Pin Configurations
/××× indicates active low signal.
µPD4482162, 4482182, 4482322, 4482362
100-pin PLASTIC LQFP (14 x 20)
[µPD4482162GF, µPD4482182GF]
Marking Side
NC
NC
NC
VDDQ
VSSQ
NC
NC
I/O9
I/O10
VSSQ
VDDQ
I/O11
I/O12
NC
VDD
NC
VSS
I/O13
I/O14
VDDQ
VSSQ
I/O15
I/O16
I/OP2, NC
NC
VSSQ
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A18
NC
NC
VDDQ
VSSQ
NC
I/OP1, NC
I/O8
I/O7
VSSQ
VDDQ
I/O6
I/O5
VSS
NC
VDD
ZZ
I/O4
I/O3
VDDQ
VSSQ
I/O2
I/O1
NC
NC
VSSQ
VDDQ
NC
NC
NC
Remark Refer to Package Drawing for the 1-pin index mark.
Data Sheet M14522EJ3V0DS
3


3Pages


UPD4482362 電子部品, 半導体
µPD4482162, 4482182, 4482322, 4482362
Pin Identification (µPD4482322GF, µPD4482362GF)
Symbol
Pin No.
Description
A0 to A17
I/O1 to I/O32
I/OP1, NC Note
I/OP2, NC Note
I/OP3, NC Note
I/OP4, NC Note
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 43
Synchronous Address Input
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, Synchronous Data In,
75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, Synchronous / Asynchronous Data Out
24, 25, 28, 29
51 Synchronous Data In (Parity),
80 Synchronous / Asynchronous Data Out (Parity)
1
30
/ADV
83
Synchronous Burst Address Advance Input
/AP 84
Synchronous Address Status Processor Input
/AC 85
Synchronous Address Status Controller Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/BWE1 to /BWE4, /BWE 93, 94, 95, 96, 87
Synchronous Byte Write Enable Input
/GW
88
Synchronous Global Write Input
/G 86
Asynchronous Output Enable Input
CLK 89
Clock Input
MODE
31
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
ZZ 64
Asynchronous Power Down State Input
VDD 15, 41, 65, 91
Power Supply
VSS 17, 40, 67, 90
Ground
VDDQ
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
VSSQ
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC 14, 16, 38, 39, 42, 66
No Connection
Note NC (No Connection) is used in the µPD4482322GF.
I/OP1 to I/OP4 are used in the µPD4482362GF.
6 Data Sheet M14522EJ3V0DS

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
UPD4482361

(UPD4482161/2181/2321/2361) 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION

NEC
NEC
UPD4482362

(UPD4482162/2182/2322/2362) 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT

NEC
NEC
UPD4482363

(UPD4482163/2183/2323/2363) 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT

NEC
NEC


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