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PDF 82559ER Data sheet ( Hoja de datos )
| Número de pieza | 82559ER | |
| Descripción | Fast Ethernet PCI Controller | |
| Fabricantes | Intel | |
| Logotipo |  |
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82559ER Fast Ethernet PCI Controller
Networking Silicon
Datasheet
Product Features
s Optimum Integration for Lowest Cost
Solution
— Integrated IEEE 802.3 10BASE-T and
100BASE-TX compatible PHY
— Glueless 32-bit PCI master interface
— 128 Kbyte Flash interface
— Thin BGA 15mm2 package
— ACPI and PCI Power Management
— Power management event on
“interesting” packets and link status
change support
— Test Access Port
s Available in extended temperature version
— Extended temperature range: -25 C to
+85 C case temperature
s High Performance Networking Functions
— Chained memory structure similar to the
82559,82558, 82557, and 82596
— Improved dynamic transmit chaining
with multiple priorities transmit queues
— Full Duplex support at both 10 and 100
Mbps
— IEEE 802.3u Auto-Negotiation support
— 3 Kbyte transmit and 3 Kbyte receive
FIFOs
— Fast back-to-back transmission support
with minimum interframe spacing
— IEEE 802.3x 100BASE-TX Flow
Control support
— Low Power Features
— Low power 3.3 V device
— Efficient dynamic standby mode
— Deep power down support
— Clockrun protocol support
Document Number: 714682-002
Revision 1.3
March 2001
1 page  
Networking Silicon — 82559ER
9.0
10.0
11.0
8.1.7 Management Data Interface Control Register........................................ 57
8.1.8 Receive Direct Memory Access Byte Count........................................... 58
8.1.9 Early Receive Interrupt........................................................................... 58
8.1.10 Flow Control Register............................................................................. 58
8.1.11 Power Management Driver Register ...................................................... 58
8.1.12 General Control Register........................................................................ 59
8.1.13 General Status Register ......................................................................... 59
8.2 Statistical Counters ............................................................................................. 60
PHY Unit Registers .......................................................................................................... 63
9.1 MDI Registers 0 - 7 ............................................................................................. 63
9.1.1 Register 0: Control Register Bit Definitions ........................................... 63
9.1.2 Register 1: Status Register Bit Definitions ............................................ 64
9.1.3 Register 2: PHY Identifier Register Bit Definitions ................................ 65
9.1.4 Register 3: PHY Identifier Register Bit Definitions ................................ 65
9.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions .... 65
9.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions .
65
9.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions .......... 66
9.2 MDI Registers 8 - 15 ........................................................................................... 66
9.3 MDI Register 16 - 31 ........................................................................................... 66
9.3.1 Register 16: PHY Unit Status and Control Register Bit Definitions ....... 66
9.3.2 Register 17: PHY Unit Special Control Bit Definitions ........................... 67
9.3.3 Register 18: PHY Address Register ....................................................... 68
9.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions
68
9.3.5 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions ...
68
9.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions .
68
9.3.7 Register 22: Receive Symbol Error Counter Bit Definitions .................. 68
9.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error
Counter Bit Definitions 69
9.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter Bit Defini-
tions 69
9.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions ..
69
9.3.11 Register 26: Equalizer Control and Status Bit Definitions ...................... 69
9.3.12 Register 27: PHY Unit Special Control Bit Definitions ........................... 69
Electrical and Timing Specifications................................................................................. 71
10.1 Absolute Maximum Ratings................................................................................. 71
10.2 DC Specifications ............................................................................................... 71
10.3 AC Specifications ................................................................................................ 74
10.4 Timing Specifications .......................................................................................... 75
10.4.1 Clocks Specifications ............................................................................. 75
10.4.2 Timing Parameters ................................................................................. 76
Package and Pinout Information ...................................................................................... 83
11.1 Package Information ........................................................................................... 83
11.2 Pinout Information ............................................................................................... 84
Datasheet
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1.0
1.1
1.2
Networking Silicon — 82559ER
Introduction
82559ER Overview
The 82559ER is part of Intel's second generation family of fully integrated 10BASE-T/100BASE-
TX LAN solutions. The 82559ER consists of both the Media Access Controller (MAC) and the
physical layer (PHY) combined into a single component solution. 82559 family members build on
the basic functionality of the 82558 and contain power management enhancements.
The 82559ER is a 32-bit PCI controller that features enhanced scatter-gather bus mastering
capabilities which enables the 82559ER to perform high-speed data transfers over the PCI bus.The
82559ER bus master capabilities enable the component to process high-level commands and
perform multiple operations, thereby off-loading communication tasks from the system CPU. Two
large transmit and receive FIFOs of 3 Kbytes each help prevent data underruns and overruns,
allowing the 82559ER to transmit data with minimum interframe spacing (IFS).
The 82559ER can operate in either full duplex or half duplex mode. In full duplex mode the
82559ER adheres to the IEEE 802.3x Flow Control specification. Half duplex performance is
enhanced by a proprietary collision reduction mechanism.
The 82559ER includes a simple PHY interface to the wire transformer at rates of 10BASE-T and
100BASE-TX, and Auto-Negotiation capability for speed, duplex, and flow control. These features
and others reduce cost, real estate, and design complexity.
The 82559ER also includes an interface to a serial (4-pin) EEPROM and a parallel interface to a
128 Kbyte Flash memory. The EEPROM provides power-on initialization for hardware and
software configuration parameters
Suggested Reading
The 82559 family of devices are designed to be compliant with PC industry power management
initiatives. This includes the ACPI, PCI Power Management Specification, Network Device Class
specification, etc. See the following publications for more information about these topics.
• PCI Specification, PCI Special Interest Group.
• Network Device Class Reference, Revision 1.0, Intel Corporation, Microsoft Corporation, and
Toshiba.
• Advanced Configuration and Power Interface (ACPI) Specification, Intel Corporation,
Microsoft Corporation, Toshiba.
• Advanced Power Management (APM) Specification, Intel Corporation and Microsoft
Corporation.
• 82559 Fast Ethernet Multifunction PCI/CardBus Controller Datasheet, Intel Corporation.
• LAN On Motherboard (LOM) Design Guide Application Note (AP-391), Intel Corporation.
• Test Access Port Applications Note (AP-393), Intel Corporation.
Datasheet
1
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 82559ER.PDF ] | |
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