PDF MT9041B Data sheet ( Hoja de datos )

Número de pieza	MT9041B
Descripción	T1/E1 System Synchronizer
Fabricantes	Mitel Networks Corporation
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No Preview Available ! Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 Interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 Interfaces • Selectable 1.544MHz, 2.048MHz or 8kHz input reference signals • Provides C1.5, C2, C3, C4, C8 and C16 output clock signals • Provides 3 different styles of 8 KHz framing pulses • Attenuates wander from 1.9 Hz Applications • Synchronization and timing control for multitrunk T1 and E1 systems • ST-BUS clock and frame pulse sources MT9041B T1/E1 System Synchronizer Advance Information DS5059 ISSUE 3 Septemner 1999 Ordering Information MT9041BP 28 Pin PLCC -40 to +85 °C Description The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a 2.048MHz, 1.544MHz, or 8kHz input reference. The MT9041B is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced, Stratum 4, and ETSI ETS 300 011. It will meet the jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, capture range and phase change slope requirements for these speciﬁcations. VDD VSS REF Phase Detector Loop Filter OSCi OSCo DCO Output Interface Circuit Mode Select Divider MS RST FS1 FS2 Figure 1 - Functional Block Diagram C1.5o C3o C2o C4o C8o C16o F0o F8o F16o 1 1 page Advance Information MT9041B All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high capacitance (e.g. 30pF) loads. Master Clock The MT9041B can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. Control and Modes of Operation The MT9041B can operate either in Normal or Freerun modes. As shown in Table 2, pin MS selects between NORMAL and FREERUN modes. MS Description of Operation 0 NORMAL 1 FREERUN Table 2 - Operating Modes Normal Mode Normal Mode is typically used when a slave clock source synchronized to the network is required. In Normal Mode, the MT9041B provides timing (C1.5o, C2o, C3o, C4o, C8o and C16o) and frame synchronization (F0o, F8o, F16o) signals, which are synchronized to reference input (REF). The input reference signal may have a nominal frequency of 8kHz, 1.544MHz or 2.048MHz. From a reset condition, the MT9041B will take up to 25 seconds for the output signal to be phase locked to the reference. The reference frequencies are selected by the frequency control pins FS2 and FS1 as shown in Table 1. Freerun Mode Freerun Mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved. In Freerun Mode, the MT9041B provides timing and synchronization signals which are based on the master clock frequency (OSCi) only, and are not synchronized to the reference signal (REF). The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a ±32ppm output clock is required, the master clock must also be ±32ppm. See Applications - Crystal and Clock Oscillator sections. MT9041B Measures of Performance The following are some synchronizer performance indicators and their corresponding deﬁnitions. Intrinsic Jitter Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a non-synchronizing mode, i.e. free running mode, by measuring the output jitter of the device. Intrinsic jitter is usually measured with various bandlimiting ﬁlters depending on the applicable standards. Jitter Tolerance Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock), in the presence of large jitter magnitudes at various jitter frequencies applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards. Jitter Transfer Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various ﬁlters depending on the applicable standards. 5 5 Page Advance Information MT9041B AC Electrical Characteristics - Performance Characteristics Sym 1 Freerun Mode accuracy with OSCi at: 0ppm 2 ±32ppm 3 ±100ppm 4 Capture range with OSCi at: 0ppm 5 ±32ppm 6 ±100ppm 7 Phase lock time 8 Output phase continuity with: 9 mode switch to Normal 10 mode switch to Freerun 11 Output phase slope † See "Notes" following AC Electrical Characteristics tables. Min -0 -32 -100 -230 -198 -130 Max +0 +32 +100 +230 +198 +130 30 200 200 45 Units Conditions/Notes† ppm 2-5 ppm 2-5 ppm 2-5 ppm 1,3-5,37 ppm 1,3-5, 37 ppm 1,3-5,37 s 1, 3-11 ns 1-11 ns 1, 3-11 us/s 1-11, 24 AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels* - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym Schmitt TTL CMOS Units 1 Threshold Voltage VT 1.5 1.5 0.5VDD 2 Rise and Fall Threshold Voltage High VHM 2.3 2.0 0.7VDD 3 Rise and Fall Threshold Voltage Low VLM 0.8 0.8 0.3VDD * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Timing for input and output signals is based on the worst Chislehurst of the combination of TTL and CMOS thresholds. * See Figure 10. V V V ALL SIGNALS tIRF, tORF Timing Reference Points tIRF, tORF Figure 10 - Timing Parameter Measurement Voltage Levels VHM VT VLM 11 11 Page

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