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P7NB80FP の電気的特性と機能

P7NB80FPのメーカーはST Microelectronicsです、この部品の機能は「 STP7NB80」です。


製品の詳細 ( Datasheet PDF )

部品番号 P7NB80FP
部品説明 STP7NB80
メーカ ST Microelectronics
ロゴ ST Microelectronics ロゴ 




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P7NB80FP Datasheet, P7NB80FP PDF,ピン配置, 機能
www.DataSheet4U.com
STP7NB80
® STP7NB80FP
N - CHANNEL 800V - 1.2- 6.5A - TO-220/TO-220FP
PowerMESHMOSFET
TYPE
VDSS
RDS(on)
ID
ST P7N B80
ST P7N B80 FP
800 V
800 V
< 1.5
< 1.5
6.5 A
6.5 A
s TYPICAL RDS(on) = 1.2
s EXTREMELY HIGH dv/dt CAPABILITY
s 100% AVALANCHE TESTED
s VERY LOW INTRINSIC CAPACITANCES
s GATE CHARGE MINIMIZED
DESCRIPTION
Using the latest high voltage MESH OVERLAY
process, STMicroelectronics has designed an
advanced family of power MOSFETs with
outstanding performances. The new patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
lowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s SWITCH MODE POWER SUPPLIES (SMPS)
s DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Sy mb o l
Parameter
VDS Drain-source Volt age (VGS = 0)
V DGR
VGS
ID
ID
IDM ()
Ptot
Drain- gate Voltage (RGS = 20 k)
Gate-source Voltage
Drain Current (continuous) at Tc = 25 oC
Drain Current (continuous) at Tc = 100 oC
Drain Current (pulsed)
Total Dissipation at Tc = 25 oC
Derating Factor
dv/dt(1) Peak Diode Recovery voltage slope
VISO
Ts tg
Insulation Withstand Voltage (DC)
Storage Temperature
Tj Max. Operating Junction Temperature
() Pulse width limited by safe operating area
( *) Limited only maximum temperature allowed
April 1999
3
2
1
TO-220
3
2
1
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
Value
Un it
STP7NB80 STP7NB80FP
800 V
800 V
± 30
V
6.5
6. 5 (* )
A
4.1
4. 1 (* )
A
26 26 A
135
1.08
40
0.32
W
W /o C
4.5 4.5 V/ns
--
2000
oC
-65 to 150
oC
150 oC
( 1) ISD 6.5A, di/dt 200 A/µs, VDD V(BR)DSS, Tj TJMAX
1/9

1 Page





P7NB80FP pdf, ピン配列
www.DataSheet4U.com
STP7NB80/FP
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbo l
td(on)
tr
Pa ram et e r
Turn-on Time
Rise Time
Qg Tot al Gate Charge
Q gs Gat e-Source Charge
Qgd Gate-Drain Charge
Test Conditions
VDD = 400 V ID = 3.5 A
RG = 4.7
VGS = 10 V
(see test circuit, figure 3)
VDD = 640 V ID = 7 A VGS = 10 V
RG = 4.7
SWITCHING OFF
Symbo l
tr (Voff)
tf
tc
Pa ram et e r
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
VDD = 640 V ID = 7 A
RG = 4.7 VGS = 10 V
(see test circuit, figure 5)
SOURCE DRAIN DIODE
Symbo l
Pa ram et e r
Test Conditions
ISD
ISDM ()
Source-drain Current
Source-drain Current
(pulsed)
VSD () Forward On Voltage
ISD = 6. 5 A VGS = 0
trr Reverse Recovery
Time
Qrr Reverse Recovery
Charge
ISD = 7 A di/dt = 100 A/µs
VDD = 100 V Tj = 150 oC
(see test circuit, figure 5)
I R RM
Reverse Recovery
Current
() Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
() Pulse width limited by safe operating area
Min.
T yp.
20
10
Max.
Unit
ns
ns
40 52 nC
10 nC
18 nC
Min.
T yp.
15
15
25
Max.
Unit
ns
ns
ns
Min.
T yp.
Max.
6.5
26
Unit
A
A
750
7.10
19
1.6
V
ns
µC
A
Safe Operating Area for TO-220
Safe Operating Area for TO-220FP
3/9


3Pages


P7NB80FP 電子部品, 半導体
www.DataSheet4U.com
STP7NB80/FP
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/9

6 Page



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共有リンク

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部品番号部品説明メーカ
P7NB80FP

STP7NB80

ST Microelectronics
ST Microelectronics


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