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82865GのメーカーはIntelです、この部品の機能は「Graphics and Memory Controller Hub」です。 |
部品番号 | 82865G |
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部品説明 | Graphics and Memory Controller Hub | ||
メーカ | Intel | ||
ロゴ | |||
このページの下部にプレビューと82865Gダウンロード(pdfファイル)リンクがあります。 Total 30 pages
Intel® 865G/865GV Chipset
Datasheet
Intel® 82865G/82865GV Graphics and Memory Controller Hub
(GMCH)
February 2004
Document Number: 252514-005
1 Page Contents
1 Introduction...........................................................................................................15
1.1 Terminology ...................................................................................................16
1.2 Related Documents .......................................................................................17
1.3 Intel® 865G Chipset System Overview ..........................................................18
1.4 Intel® 82865G GMCH Overview ....................................................................20
1.4.1 Host Interface....................................................................................20
1.4.2 System Memory Interface .................................................................20
1.4.3 Hub Interface ....................................................................................21
1.4.4 Communications Streaming Architecture (CSA) Interface ................21
1.4.5 Multiplexed AGP and Intel® DVO Interface.......................................21
1.4.6 Graphics Overview............................................................................22
1.4.7 Display Interface ...............................................................................24
1.5 Clock Ratios...................................................................................................24
2 Signal Description ..............................................................................................25
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
Host Interface Signals....................................................................................27
Memory Interface ...........................................................................................30
2.2.1 DDR SDRAM Channel A ..................................................................30
2.2.2 DDR SDRAM Channel B ..................................................................31
Hub Interface .................................................................................................32
Communication Streaming Architecture (CSA) Interface...............................32
AGP Interface ................................................................................................33
2.5.1 AGP Addressing Signals...................................................................33
2.5.2 AGP Flow Control Signals ................................................................34
2.5.3 AGP Status Signals ..........................................................................34
2.5.4 AGP Strobes .....................................................................................35
2.5.5 PCI Signals–AGP Semantics............................................................36
2.5.6
2.5.7
2.5.5.1 PCI Pins during PCI Transactions on AGP Interface ........37
Multiplexed Intel® DVOs on AGP ......................................................37
Intel® DVO-to-AGP Pin Mapping.......................................................39
Analog Display Interface ................................................................................40
Clocks, Reset, and Miscellaneous Signals ....................................................41
RCOMP, VREF, VSWING Signals.................................................................42
Power and Ground Signals ............................................................................43
GMCH Sequencing Requirements.................................................................44
Signals Used As Straps .................................................................................45
2.11.1 Functional Straps ..............................................................................45
2.11.2 Strap Input Signals............................................................................45
Full and Warm Reset States ..........................................................................46
3 Register Description..........................................................................................47
3.1 Register Terminology.....................................................................................47
3.2 Platform Configuration Structure....................................................................48
3.3 Routing Configuration Accesses....................................................................50
3.3.1 Standard PCI Bus Configuration Mechanism ...................................50
3.3.2 PCI Bus #0 Configuration Mechanism ..............................................50
3.3.3 Primary PCI and Downstream Configuration Mechanism.................50
3.3.4 AGP/PCI_B Bus Configuration Mechanism ......................................51
Intel® 82865G/82865GV GMCH Datasheet
3
3Pages 3.8
3.9
3.10
PCI-to-CSA Bridge Registers (Device 3) ..................................................... 113
3.8.1 VID3—Vendor Identification Register (Device 3)............................ 114
3.8.2 DID3—Device Identification Register (Device 3) ............................ 114
3.8.3 PCICMD3—PCI Command Register (Device 3)............................. 115
3.8.4 PCISTS3—PCI Status Register (Device 3) .................................... 116
3.8.5 RID3—Revision Identification Register (Device 3) ......................... 117
3.8.6 SUBC3—Class Code Register (Device 3) ...................................... 117
3.8.7 BCC3—Base Class Code Register (Device 3) ............................... 117
3.8.8 MLT3—Master Latency Timer Register (Device 3)......................... 118
3.8.9 HDR3—Header Type Register (Device 3) ...................................... 118
3.8.10 PBUSN3—Primary Bus Number Register (Device 3)..................... 118
3.8.11 SBUSN3—Secondary Bus Number Register (Device 3) ................ 119
3.8.12 SMLT3—Secondary Bus Master Latency Timer Register
(Device 3) ....................................................................................... 119
3.8.13 IOBASE3—I/O Base Address Register (Device 3) ......................... 120
3.8.14 IOLIMIT3—I/O Limit Address Register (Device 3) .......................... 120
3.8.15 SSTS3—Secondary Status Register (Device 3)............................. 121
3.8.16 MBASE3—Memory Base Address Register (Device 3).................. 122
3.8.17 MLIMIT3—Memory Limit Address Register (Device 3)................... 123
3.8.18 PMBASE3—Prefetchable Memory Base Address Register
(Device 3) ....................................................................................... 124
3.8.19 PMLIMIT3—Prefetchable Memory Limit Address Register
(Device 3) ....................................................................................... 124
3.8.20 BCTRL3—Bridge Control Register (Device 3)................................ 125
3.8.21 ERRCMD3—Error Command Register (Device 3) ......................... 126
3.8.22 CSACNTRL—CSA Control Register (Device 3) ............................. 126
Overflow Configuration Registers (Device 6)............................................... 127
3.9.1 VID6—Vendor Identification Register (Device 6)............................ 127
3.9.2 DID6—Device Identification Register (Device 6) ............................ 128
3.9.3 PCICMD6—PCI Command Register (Device 6)............................. 128
3.9.4 PCISTS6—PCI Status Register (Device 6) .................................... 129
3.9.5 RID6—Revision Identification Register (Device 6) ......................... 129
3.9.6 SUBC6—Sub-Class Code Register (Device 6) .............................. 130
3.9.7 BCC6—Base Class Code Register (Device 6) ............................... 130
3.9.8 HDR6—Header Type Register (Device 6) ...................................... 130
3.9.9 BAR6—Memory Delays Base Address Register (Device 6)........... 131
3.9.10 SVID6—Subsystem Vendor Identification Register
(Device 6) ....................................................................................... 131
3.9.11 SID6—Subsystem Identification Register (Device 6)...................... 131
Device 6 Memory-Mapped I/O Register Space ........................................... 132
3.10.1 DRB[0:7]—DRAM Row Boundary Register
(Device 6, MMR) ............................................................................. 132
3.10.2 DRA—DRAM Row Attribute Register (Device 6, MMR) ................. 134
3.10.3 DRT—DRAM Timing Register (Device 6, MMR) ............................ 135
3.10.4 DRC—DRAM Controller Mode Register (Device 6, MMR) ............. 136
4 System Address Map ...................................................................................... 139
4.1 System Memory Address Ranges ............................................................... 139
4.2 Compatibility Area........................................................................................ 141
4.3 Extended Memory Area ............................................................................... 143
4.3.1 15 MB–16 MB Window ................................................................... 143
4.3.2 Pre-Allocated Memory .................................................................... 144
6 Intel® 82865G/82865GV GMCH Datasheet
6 Page | |||
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部品番号 | 部品説明 | メーカ |
82865G | Graphics and Memory Controller Hub | Intel |
82865GV | Graphics and Memory Controller Hub | Intel |