PDF MT933 Data sheet ( Hoja de datos )

Número de pieza	MT933
Descripción	3.3V 10/100 Fast Ethernet Transceiver to MII
Fabricantes	Zarlink Semiconductor
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No Preview Available ! This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ 1 page MT933 TX100 PISO, Encoder and Scrambler Data from the MII is loaded into the TX100 PISO, Encoder and Scrambler on the rising edge of TX_CLK. It is converted to serial MLT3 for outputting to the TX100 Driver. The TXD[3] bit is output first. The PISO & Encoder do not operate until the 125MHz Synthesizer is locked to the 25MHz reference. This avoids transmission of spurious signals onto the twisted-pair. TX100 Driver The TX100 Driver outputs the differential signal onto the TXOP and TXON pins. It operates with 1:root 2 magnetics to provide impedance matching and amplification of the signal in accordance with the 802.3 specifications. The transmit current is governed by the current through the TXREF100 pin, which must be grounded through a resistor as described in “External Components”. The TX100 driver is disabled in 10BASE-T mode and in loop back mode.If no data is being transmitted from the MAC, the MT933 outputs idle symbols of 11111 (suitably scrambled). TX100 Latency The transmit latency from the first TX_CLK rising when TX_EN is high to the first bit of the “J” symbol on the cable is 8BT. RX100 Equalizer & Base-line Wander Correction The RX100 Equalizer compensates for the signal attenuation and distortion resulting from transmission down the cable and through the isolation transformers. The Equalizer is self-adjusting and is designed to restore signals received from up to 10dB cable attenuation (at 16MHz). When the Equalizer is active it adjusts to the incoming signal within 1ms. Thereafter, the Equalizer will continuously adjust to small variations in signal level without corrupting the received data. The 100BASE-TX MLT3 code contains significant low frequency components which are not passed through the isolation transformers and cannot be restored by an adaptive equalizer. This leads to a phenomenon known as Base-line Wander which will cause an unacceptable increase in error rate if not corrected. The MT933 employs a quantized feedback technique to restore the low frequency components and thus maintain a very low error rate even when receiving signals such as the “killer packet” described in the TP_PMD spec. RX100 Clock Recovery The RX100 Clock Recovery circuit uses a Phase- Locked Loop (PLL) to derive a sampling clock from the incoming signal. The recovered clock runs at the symbol bit rate rate (nominally 125MHz) and is used to clock the MLT3 decoder and the Serial to Parallel converter (SIPO). The recovered clock is divided by 5 to generate the receive clock (RX_CLK) which is used to strobe received data across the MII interface. When no signal is detected in 100BASE-TX mode, the PLL is locked to the reference clock and runs at 125MHz. This ensures that RX_CLK runs continuously at 25MHz in 100BASE-TX mode. When a signal is present, the Clock Recovery PLL remains locked to the reference until the equalizer has adjusted, then it requires up to 1ms to phase lock to the incoming signal. No data is passed to the MII interface until lock is established. RX100 SIPO, Decoder and Descrambler The RX100 SIPO, Decoder and Descrambler convert the received signal from serial MLT3 to 4-bit wide parallel receive data on the MII. This appears on the RXD[3:0] bus which is clocked out on the falling edge of RX_CLK. When a frame starts the MT933 decodes the SSD symbols and then asserts the RX_DV signal, in order to inform the MAC that valid data is available. When the MT933 detects the ESD, it deasserts the RX_DV signal. RX100 Latency The latency from the first bit of the “J” symbol on the cable to CRS assertion is between 11 and 15BT. The latency from the first bit of the “T” symbol on the cable to CRS de-assertion is between 19 and 23BT. 100Mb/s Transmit Errors If the MT933 detects that the TX_ER signal has gone active whilst the TX_EN signal is active, then it will propagate the detected error onto the cable by transmitting the symbol “00100” . Figure 3 shows the meaning of the different states of TX_EN and TX_ER. TX_ER is sampled inside the MT933 on the rising edge of TX_CLK. 4 5 Page MT933 reg 1- status register Bit Bit name Description Default 1.15 1.14 1.13 1.12 1.11 1.10 1.9 1.8:7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 100BaseT4 100BASE-TX - FDX 100BASE-TX - HDX 10BASE-T - FDX 10BASE-T - HDX 100BaseT2 - FDX 100BaseT2 - HDX Reserved MF preamble suppression ANEG complete Remote fault ANEG able Link status Jabber detect Extended regs 1 = PHY able to perform 100BaseT4 0 = PHY not able to perform 100BaseT4 1 = PHY able to perform 100BASE-TX 0 = PHY not able to perform 100BASE-TX 1 = PHY able to perform 100BASE-TX 0 = PHY not able to perform 100BASE-TX 1 = PHY able to perform 10BASE-T 0 = PHY not able to perform 10BASE-T 1 = PHY able to perform 10BASE-T 0 = PHY not able to perform 10BASE-T 1 = PHY able to perform 100BaseT2 0 = PHY not able to perform 100BaseT2 1 = PHY able to perform 100BaseT2 0 = PHY not able to perform 100BaseT2 ignore when read 1= Phy accept management frames with short preamble 0 = normal preamble only 1 = ANEG process completed 0 = ANEG process not completed or not active 1= Remote fault condition detected 0 = no Remote fault condition detected 1 = Phy is able to perform ANEG 0 = Phy is not able to perform ANEG 1= Link is up 0 = Link is down 1 = jabber condition detected 0 = normal operation 1 = extended register capability 0 = no extended registers 0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 R/W RO RO RO RO RO RO RO RO RO RO RO LH RO RO LL RO RO reg 2/3- MT933 Identifier register Bit 2.15:0 3.15:0 Bit name OUI OUI/device ID Description Mitel OUI bits Mitel OUI bits and device code Default 0282 1C7X R/W RO RO 10 11 Page

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