PDF MT8941 Data sheet ( Hoja de datos )

Número de pieza	MT8941
Descripción	CMOS ST-BUS FAMILY Advanced T1/CEPT Digital Trunk PLL
Fabricantes	Mitel Networks Corporation
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No Preview Available ! CMOS ST-BUS™ FAMILY MT8941 ® Advanced T1/CEPT Digital Trunk PLL Features • Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock (frame pulse) • Provides CEPT clock at 2.048 MHz and ST- BUS clock and timing signals locked to an internal or external 8 kHz reference clock • Typical inherent output jitter (unfiltered)= 0.07 UI peak-to-peak • Typical jitter attenuation at: 10 Hz=23 dB,100 Hz=43 dB, 5 to 40 kHz ≥ 64 dB • Jitter-free “FREE-RUN” mode • Uncommitted two-input NAND gate • Low power CMOS technology Applications • Synchronization and timing control for T1 and CEPT digital trunk transmission links • ST- BUS clock and frame pulse source ISSUE 5 Ordering Information July 1993 MT8941AE MT8941AP 24 Pin Plastic DIP 28 Pin PLCC -40°C to +85°C Description The MT8941 is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmission link and the ST-BUS are provided by the second PLL locked to an internal or an external 8 kHz frame pulse signal. The MT8941 offers improved jitter performance over the MT8940. The two devices also have some functional differences, which are listed in the section on “Differences between MT8941 and MT8940”. F0i C12i MS0 MS1 MS2 MS3 C8Kb C16i Ai Bi DPLL #1 Mode Selection Logic DPLL #2 2:1 MUX Input Selector Clock Generator Variable Clock Control Frame Pulse Control 4.096 MHz Clock Control 2.048 MHz Clock Control Yo VDD VSS RST Figure 1 - Functional Block Diagram CVb CV ENCV F0b C4b C4o ENC4o C2o C2o ENC2o 3-43 1 page CMOS MT8941 at 8 kHz to generate T1 (1.544 MHz) clock. For DPLL #2, the divisions are set at 8 and 256 to provide the CEPT/ST-BUS clock at 2.048 MHz synchronized to the falling edge of the input signal (8 kHz). The master clock source is specified to be 12.352 MHz for DPLL #1 and 16.384 MHz for DPLL #2 over the entire temperature range of operation. The inputs MS0 to MS3 are used to select the operating mode of the MT8941, see Tables 1 to 4. All the outputs are controlled to the high impedance condition by their respective enable controls. The uncommitted NAND gate is available for use in applications involving Mitel’s MT8976/ MH89760 (T1 Interfaces) and MT8979/MH89790 (CEPT Interfaces). Modes of Operation The operation of the MT8941 is categorized into major modes and minor modes. The major modes are defined for both DPLLs by the mode select pins MS0 and MS1. The minor modes are selected by pins MS2 and MS3 and are applicable only to DPLL #2. There are no minor modes for DPLL #1. Major modes of DPLL #1 DPLL #1 can be operated in three major modes as selected by MS0 and MS1 (Table 1). When MS1 is LOW, it is in NORMAL mode, which provides a T1 (1.544 MHz) clock signal locked to the falling edge of the input frame pulse F0i (8 kHz). DPLL #1 requires a master clock input of 12.352 MHz (C12i). In the second and third major modes (MS1 is HIGH), DPLL #1 is set to DIVIDE an external 1.544 MHz or 2.048 MHz signal applied at CVb (pin 21). The division can be set by MS0 to be either 193 (LOW) or 256 (HIGH). In these modes, the 8 kHz output at C8Kb is connected internally to DPLL #2, which operates in SINGLE CLOCK mode. Major modes of DPLL #2 There are four major modes for DPLL #2 selectable by MS0 and MS1, as shown in Table 2. In all these modes DPLL #2 provides the CEPT PCM30 timing, and the ST-BUS clock and framing signals. In NORMAL mode, DPLL #2 provides the CEPT/ST- BUS compatible timing signals locked to the falling edge of the 8 kHz input signal (C8Kb). These signals are 4.096 MHz (C4o and C4b) and 2.048 MHz (C2o and C2o) clocks, and the 8 kHz frame pulse (F0b) derived from the 16.384 MHz master clock. This mode can be the same as the FREE- RUN mode if the C8Kb pin is tied to VDD or VSS. M S 0 M S 1 Mode of Operation Function X0 Provides the T1 (1.544 MHz) clock NORMAL synchronized to the falling edge of the input frame pulse (F0i). DPLL #1 divides the CVb input by 0 1 DIVIDE-1 193. The divided output is connected to DPLL #2. DPLL #1 divides the CVb input by 1 1 DIVIDE-2 256. The divided output is connected to DPLL #2. Note: X: indicates don’t care Table 1. Major Modes of DPLL #1 MM SS 01 Mode of Operation Function 00 Provides CEPT/ST-BUS timing NORMAL signals locked to the falling edge of the 8 kHz input signal at C8Kb. Provides CEPT/ST-BUS timing and 1 0 FREE-RUN framing signals with no external inputs, except the master clock. 01 SINGLE CLOCK-1 Provides CEPT/ST-BUS timing signals locked to the falling edge of the 8 kHz internal signal provided by DPLL #1. 11 SINGLE CLOCK-2 Provides CEPT/ST-BUS timing signals locked to the falling edge of the 8 kHz internal signal provided by DPLL #1. Table 2. Major Modes of DPLL #2 MM SS 23 Functional Description Provides CEPT/ST-BUS 4.096 MHz and 2.048 1 1 MHz clocks and 8kHz frame pulse depending on the major mode selected. Provides CEPT/ST-BUS 4.096 MHz & 2.048 MHz clocks depending on the major mode selected 0 1 while F0b acts as an input. However, the input on F0b has no effect on the operation of DPLL #2 unless it is in FREE-RUN mode. Overrides the major mode selected and accepts 0 0 properly phase related external 4.096 MHz clock and 8 kHz frame pulse to provide the ST-BUS compatible clock at 2.048 MHz. Overrides the major mode selected and accepts a 1 0 4.096 MHz external clock to provide the ST-BUS clock and frame pulse at 2.048 MHz and 8 kHz, respectively. Table 3. Minor Modes of DPLL #2 In FREE-RUN mode, DPLL #2 generates the stand- alone CEPT and ST-BUS timing and framing signals with no external inputs except the master clock set at 16.384 MHz. The DPLL makes no correction in this configuration and provides the timing signals without any jitter. 3-47 5 Page CMOS MT8941 Crystal Clock (12.352 MHz) Crystal Clock (16.384 MHz) MT8941 MS0 MS1 MS2 MS3 F0i C12i ENCV C8Kb C16i ENC4o ENC2o VDD CVb C4b C2o F0b VSS RST C R VDD MT8980/81 MH89760B C1.5i C2i F0i E8Ko DSTi DSTo CSTi CSTo TxT TxR RxT RxR TRANSMIT RECEIVE ST-BUS SWITCH T1 LINK (1.544 Mbps) Mode of Operation for the MT8941 DPLL #1 - NORMAL ( MS1=0) DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1) Figure 10 - Synchronization at the Slave End of the T1 Transmission Link Crystal Clock (16.384 MHz) MT8941 MS0 MS1 MS2 MS3 F0i C12i ENCV C8Kb C16i ENC4o ENC2o VDD C4b C2o F0b VSS RST Yo MH89790B DSTi C2i DSTo F0i CSTi0 CSTi1 CSTo OUTA OUTB TRANSMIT RxT RECEIVE RxR MT8980/81 ST-BUS SWITCH CEPT PRIMARY MULTIPLEX DIGITAL LINK VDD Mode of Operation for the MT8941 CR DPLL #1 - NOT USED DPLL #2 - FREE-RUN (MS0=1; MS1=0; MS2=1; MS3=1) Figure 11 - Synchronization at the Master End of the CEPT Digital Transmission Link At the slave end of the link (Figure 10) both the DPLLs are in NORMAL mode, with DPLL #2 providing the ST-BUS timing signals locked to the 8 kHz frame pulse (E8Ko) extracted from the received signal on the T1 line. The regenerated frame pulse is looped back to DPLL #1 to provide the T1 line clock, which is the same as the master end. The 12.352 MHz and 16.384 MHz crystal clock sources are necessary for DPLL #1 and #2, respectively. Synchronization and Timing Signals for the CEPT Transmission Link The MT8941 can be used to provide the timing and synchronization signals for the MH89790/790B, Mitel’s CEPT (30+2) Digital Trunk Interface Hybrid. Since the operational frequencies of the ST-BUS and the CEPT primary multiplex digital trunk are the same, only DPLL #2 is required. 3-53 11 Page

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