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PDF MT8941B Data sheet ( Hoja de datos )
| Número de pieza | MT8941B | |
| Descripción | Advanced T1/CEPT Digital Trunk PLL | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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MT8941B
Advanced T1/CEPT Digital Trunk PLL
Data Sheet
Features
• Provides T1 clock at 1.544 MHz locked to an 8
kHz reference clock (frame pulse)
• Provides CEPT clock at 2.048 MHz and ST-BUS
clock and timing signals locked to an internal or
external 8 kHz reference clock
• Typical inherent output jitter (unfiltered)= 0.07 UI
peak-to-peak
• Typical jitter attenuation at: 10 Hz=23 dB,100
Hz=43 dB, 5 to 40 kHz ≥ 64 dB
• Jitter-free “FREE-RUN” mode
• Uncommitted two-input NAND gate
• Low power CMOS technology
Applications
• Synchronization and timing control for T1
and CEPT digital trunk transmission links
• ST- BUS clock and frame pulse source
February 2005
Ordering Information
MT8941BE 24 Pin PDIP Tubes
MT8941BP 28 Pin PLCC Tubes
MT8941BPR 28 Pin PLCC Tape & Reel
MT8941BP1 28 Pin PLCC* Tubes
MT8941BPR1 28 Pin PLCC* Tape & Reel
*Pb Free Matte Tin
-40°C to +85°C
Description
The MT8941B is a dual digital phase-locked loop
providing the timing and synchronization signals for the
T1 or CEPT transmission links and the ST-BUS. The
first PLL provides the T1 clock (1.544 MHz)
synchronized to the input frame pulse at 8 kHz. The
timing signals for the CEPT transmission link and the
ST-BUS are provided by the second PLL locked to an
internal or an external 8 kHz frame pulse signal.
The MT8941B offers improved jitter performance over
the MT8940. The two devices also have some
functional differences, which are listed in the section on
“Differences between MT8941B and MT8940”.
F0i
C12i
MS0
MS1
MS2
MS3
C8Kb
C16i
Ai
Bi
DPLL #1
Mode
Selection
Logic
DPLL #2
2:1 MUX
Input
Selector
Clock
Generator
Variable
Clock
Control
Frame Pulse
Control
4.096 MHz
Clock
Control
2.048 MHz
Clock
Control
Yo VDD VSS RST
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
CVb
CV
ENCV
F0b
C4b
C4o
ENC4o
C2o
C2o
ENC2o
1 page  
MT8941B
Data Sheet
Input-to-Output Phase Relationship
The no-correction window size is 324 ns for DPLL #1 and 32 µs for DPLL #2. It is possible for the relative phase of
the reference signal to swing inside the no-correction window depending on its jitter and the relative drift of the
master clock. As a result, the phase relationship between the input signal and the output clocks (and frame pulse in
case of DPLL #2) may vary up to a maximum of window size. This situation is illustrated in Figure 4. The maximum
phase variation for DPLL #1 is 324 ns and for DPLL #2 it is 32 µs. However, this phase difference can be absorbed
by the input jitter buffer of Zarlink’s T1/CEPT devices.
The no-correction window acts as a filter for low frequency jitter and wander since the DPLL does not track the
reference signal inside it. The size of the no-correction window is less than or equal to the size of the input jitter
buffer on the T1 and CEPT devices to guarantee that no slip will occur in the received T1/CEPT frame.
The circuit will remain in synchronization as long as the input frequency is within the lock-in range of the DPLLs
(refer to the section on “Jitter Performance and Lock-in Range” for further details). The lock-in range is wide enough
to meet the CCITT line rate specification (1.544 MHz ±32 ppm and 2.048 MHz ±50 ppm) for the High Capacity
Terrestrial Digital Service.
The phase sampling is done once in a frame (8 kHz) for each DPLL. The divisions are set at 8 and 193 for DPLL #1,
which locks to the falling edge of the input at 8 kHz to generate T1 (1.544 MHz) clock. For DPLL #2, the divisions
are set at 8 and 256 to provide the CEPT/ST-BUS clock at 2.048 MHz synchronized to the falling edge of the input
signal (8 kHz). The master clock source is specified to be 12.352 MHz for DPLL #1 and 16.384 MHz for DPLL #2
over the entire temperature range of operation.
The inputs MS0 to MS3 are used to select the operating mode of the MT8941B, see Tables 1 to 4. All the outputs
are controlled to the high impedance condition by their respective enable controls. The uncommitted NAND gate is
available for use in applications involving Zarlink’s MT8976/ MH89760 (T1 Interfaces) and MT8979/MH89790
(CEPT Interfaces).
Modes of Operation
The operation of the MT8941B is categorized into major modes and minor modes. The major modes are defined for
both DPLLs by the mode select pins MS0 and MS1. The minor modes are selected by pins MS2 and MS3 and are
applicable only to DPLL #2. There are no minor modes for DPLL #1.
Major modes of DPLL #1
DPLL #1 can be operated in three major modes as selected by MS0 and MS1 (Table 1). When MS1 is LOW, it is in
NORMAL mode, which provides a T1 (1.544 MHz) clock signal locked to the falling edge of the input frame pulse
F0i (8 kHz). DPLL #1 requires a master clock input of 12.352 MHz (C12i). In the second and third major modes
(MS1 is HIGH), DPLL #1 is set to DIVIDE an external 1.544 MHz or 2.048 MHz signal applied at CVb (pin 21). The
division can be set by MS0 to be either 193 (LOW) or 256 (HIGH). In these modes, the 8 kHz output at C8Kb is
connected internally to DPLL #2, which operates in SINGLE CLOCK mode.
Major modes of DPLL #2
There are four major modes for DPLL #2 selectable by MS0 and MS1, as shown in Table 2. In all these modes
DPLL #2 provides the CEPT PCM30 timing, and the ST-BUS clock and framing signals.
In NORMAL mode, DPLL #2 provides the CEPT/ST-BUS compatible timing signals locked to the falling edge of the
8 kHz input signal (C8Kb). These signals are 4.096 MHz (C4o and C4b) and 2.048 MHz (C2o and C2o) clocks, and
the 8 kHz frame pulse (F0b) derived from the 16.384 MHz master clock. This mode can be the same as the FREE-
RUN mode if the C8Kb pin is tied to VDD or VSS.
5
Zarlink Semiconductor Inc.
5 Page 
MT8941B
Data Sheet
Figure 6 - The Jitter Transfer Function for PLL1
Figure 7 - The Jitter Transfer Function for PLL2
However, if DPLL #1 and DPLL #2 are daisy-chained as shown in Figures 9 and 10, the output clock tolerance of
DPLL #1 will be equal to that of the DPLL #2 oscillator when DPLL #2 is free-running. In this case, the oscillator
tolerance of DPLL #1 has no impact on its output clock tolerance. For this reason, it is recommended to use a
±32 ppm oscillator for DPLL #2 and a ±100 ppm oscillator for DPLL #1.
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet MT8941B.PDF ] | |
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