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P9NB60FPのメーカーはST Microelectronicsです、この部品の機能は「 STP9NB60FP」です。 |
部品番号 | P9NB60FP |
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部品説明 | STP9NB60FP | ||
メーカ | ST Microelectronics | ||
ロゴ | |||
このページの下部にプレビューとP9NB60FPダウンロード(pdfファイル)リンクがあります。 Total 9 pages
STP9NB60
® STP9NB60FP
N - CHANNEL 600V - 0.7Ω - 9A TO-220/TO220FP
PowerMESH™ MOSFET
TYPE
VDSS
RDS(on)
ID
ST P9N B60
ST P9N B60 FP
600 V
600 V
< 0.8 Ω
< 0.8 Ω
9.0 A
9.0 A
s TYPICAL RDS(on) = 0.7 Ω
s EXTREMELY HIGH dv/dt CAPABILITY
s 100% AVALANCHE TESTED
s VERY LOW INTRINSIC CAPACITANCES
s GATE CHARGE MINIMIZED
DESCRIPTION
Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an
advanced family of power MOSFETs with
outstanding performances. The new patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
lowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
3
2
1
TO-220
3
2
1
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s SWITCH MODE POWER SUPPLIES (SMPS)
s DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Sy mb o l
Parameter
V DS
V DGR
VGS
ID
ID
IDM (•)
Ptot
Drain-source Voltage (VGS = 0)
Drain- gate Voltage (RGS = 20 kΩ)
Gate-source Voltage
Drain Current (cont inuous) at Tc = 25 oC
Drain Current (cont inuous) at Tc = 100 oC
Drain Current (pulsed)
Total Dissipation at Tc = 25 oC
Derating F actor
dv/dt(1) Peak Diode Recovery voltage slope
VISO Insulation Withstand Voltage (DC)
Ts tg St orage Temperature
Tj Max. Operating Junction Temperature
(•) Pulse width limited by safe operating area
(*) Limited only by maximum temperature allowed
January 2000
Value
STP9NB60 STP9NB60FP
600
600
± 30
9.0 9.0(*)
5.7 5.7(*)
36 36
125 40
1.0 0.32
4.5 4.5
2000
-65 to 150
150
( 1) ISD ≤ 9A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
Un it
V
V
V
A
A
A
W
W /o C
V/ns
V
oC
oC
1/9
1 Page STP9NB60/FP
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbo l
td(on)
tr
Pa ram et e r
Turn-on Time
Rise Time
Qg Tot al Gate Charge
Q gs Gat e-Source Charge
Qgd Gate-Drain Charge
Test Conditions
VDD = 300 V ID = 4.5 A
RG = 4.7 Ω
VGS = 10 V
(see test circuit, figure 3)
VDD = 480 V ID = 9.0 A VGS = 10 V
Min.
T yp.
25
11
40
10.5
17.5
Max.
35
15
56
Unit
ns
ns
nC
nC
nC
SWITCHING OFF
Symbo l
tr (Voff)
tf
tc
Pa ram et e r
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
VDD = 480 V ID = 9.0 A
RG = 4.7 Ω VGS = 10 V
(see test circuit, figure 5)
Min.
T yp.
12
10
21
Max.
17
14
29
Unit
ns
ns
ns
SOURCE DRAIN DIODE
Symbo l
Pa ram et e r
Test Conditions
ISD
ISDM (•)
Source-drain Current
Source-drain Current
(pulsed)
VSD (∗) Forward On Voltage
ISD = 9. 0 A VGS = 0
trr Reverse Recovery
Time
Qrr Reverse Recovery
Charge
ISD = 9.0 A di/dt = 100 A/µs
VDD = 100 V Tj = 150 oC
(see test circuit, figure 5)
I R RM
Reverse Recovery
Current
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Min.
T yp.
Max.
9.0
36
Unit
A
A
1.6
600
5.4
18
V
ns
µC
A
Safe Operating Area for TO-220
Safe Operating Area for TO-220FP
3/9
3Pages STP9NB60/FP
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/9
6 Page | |||
ページ | 合計 : 9 ページ | ||
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データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
P9NB60FP | STP9NB60FP | ST Microelectronics |