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MTD20N06HDのメーカーはMotorola Semiconductorsです、この部品の機能は「TMOS POWER FET 20 AMPERES 60 VOLTS RDS(on) = 0.045 OHM」です。 |
部品番号 | MTD20N06HD |
| |
部品説明 | TMOS POWER FET 20 AMPERES 60 VOLTS RDS(on) = 0.045 OHM | ||
メーカ | Motorola Semiconductors | ||
ロゴ | |||
このページの下部にプレビューとMTD20N06HDダウンロード(pdfファイル)リンクがあります。 Total 12 pages
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTD20N06HD/D
™Designer's Data Sheet
HDTMOS E-FET.™
Power Field Effect Transistor
DPAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
This advanced HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
G
MTD20N06HD
Motorola Preferred Device
TMOS POWER FET
20 AMPERES
60 VOLTS
RDS(on) = 0.045 OHM
™
D
CASE 369A–13, Style 2
DPAK
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VDSS 60 Vdc
VDGR 60 Vdc
VGS
± 20 Vdc
VGSM ± 30 Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID 20 Adc
ID 16
IDM 60 Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size
PD 40 Watts
0.32 W/°C
1.75 Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 0.3 mH, RG = 25 Ω)
EAS 60 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
RθJC
RθJA
RθJA
3.13 °C/W
100
71.4
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
©MMoottoororolal,aInTc.M19O9S5 Power MOSFET Transistor Device Data
1
1 Page TYPICAL ELECTRICAL CHARACTERISTICS
MTD20N06HD
40
VGS = 10 V
32
24
16
9V
8V
7V
TJ = 25°C
6V
40
VDS ≥ 10 V
30
20
8 5V
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDS, DRAIN–TO–SOURCE VOLTAGE (Volts)
Figure 1. On–Region Characteristics
10
100°C
25°C
0
2 34
TJ = – 55°C
56
7
VGS, GATE–TO–SOURCE VOLTAGE (Volts)
Figure 2. Transfer Characteristics
8
0.052
VGS = 10 V
0.048
0.044
TJ = 100°C
0.040
0.036
25°C
0.032
0.028
0.024
– 55°C
0.020
0
10 20 30
ID, DRAIN CURRENT (Amps)
40
Figure 3. On–Resistance versus Drain Current
and Temperature
0.040
0.038
TJ = 25°C
0.036
VGS = 10 V
0.034
0.032
15 V
0.030
0.028
0
10 20
30
ID, DRAIN CURRENT (Amps)
40
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1.6
VGS = 10 V
1.4 ID = 10 A
1.2
1.0
0.8
0.6
– 50 – 25
0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation with
Temperature
Motorola TMOS Power MOSFET Transistor Device Data
3
3Pages MTD20N06HD
di/dt = 300 A/µs
Standard Cell Density
trr
High Cell Density
trr
ta tb
t, TIME
Figure 10. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance – Gen-
eral Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy
rating must be derated for temperature as shown in the ac-
companying graph (Figure 12). Maximum energy at currents
below rated continuous ID can safely be assumed to equal
the values indicated.
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 µs
10 100 µs
1.0
0.1
0.1
1 ms
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1.0 10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
100
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
60
ID = 20 A
50
40
30
20
10
0
25 50
75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
6 Motorola TMOS Power MOSFET Transistor Device Data
6 Page | |||
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部品番号 | 部品説明 | メーカ |
MTD20N06HD | TMOS POWER FET 20 AMPERES 60 VOLTS RDS(on) = 0.045 OHM | Motorola Semiconductors |
MTD20N06HDL | TMOS POWER FET LOGIC LEVEL 20 AMPERES 60 VOLTS RDS(on) = 0.045 OHM | Motorola Semiconductors |