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PDF 20N03HL Data sheet ( 特性 )

部品番号 20N03HL
部品説明 MTD20N03HL
メーカ Motorola Semiconductors
ロゴ Motorola Semiconductors ロゴ 

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20N03HL Datasheet, 20N03HL PDF,ピン配置, 機能
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTD20N03HDL/D
Designer's
Data Sheet
HDTMOS E-FET .
High Density Power FET
DPAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
This advanced HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
www.DataSheet4cUo.nctormols, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a Dis-
crete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
G
D
S
MTD20N03HDL
Motorola Preferred Device
TMOS POWER FET
LOGIC LEVEL
20 AMPERES
30 VOLTS
RDS(on) = 0.035 OHM
CASE 369A–13, Style 2
DPAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 M)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp 10 ms)
VDSS 30 Vdc
VDGR 30 Vdc
VGS
±15 Vdc
VGSM ± 20 Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
ID 20 Adc
ID 16
IDM 60 Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C, when mounted with the minimum recommended pad size
PD 74 Watts
0.6 W/°C
1.75
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 )
EAS 200 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
RθJC
RθJA
RθJA
1.67 °C/W
100
71.4
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET, and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
© MMoototororloa,laIncT.M19O95S Power MOSFET Transistor Device Data
1

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