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20N03HL の電気的特性と機能

20N03HLのメーカーはMotorola Semiconductorsです、この部品の機能は「MTD20N03HL」です。


製品の詳細 ( Datasheet PDF )

部品番号 20N03HL
部品説明 MTD20N03HL
メーカ Motorola Semiconductors
ロゴ Motorola Semiconductors ロゴ 




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20N03HL Datasheet, 20N03HL PDF,ピン配置, 機能
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTD20N03HDL/D
Designer's
Data Sheet
HDTMOS E-FET .
High Density Power FET
DPAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
This advanced HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
www.DataSheet4cUo.nctormols, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a Dis-
crete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
G
D
S
MTD20N03HDL
Motorola Preferred Device
TMOS POWER FET
LOGIC LEVEL
20 AMPERES
30 VOLTS
RDS(on) = 0.035 OHM
CASE 369A–13, Style 2
DPAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 M)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp 10 ms)
VDSS 30 Vdc
VDGR 30 Vdc
VGS
±15 Vdc
VGSM ± 20 Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
ID 20 Adc
ID 16
IDM 60 Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C, when mounted with the minimum recommended pad size
PD 74 Watts
0.6 W/°C
1.75
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 )
EAS 200 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
RθJC
RθJA
RθJA
1.67 °C/W
100
71.4
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET, and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
© MMoototororloa,laIncT.M19O95S Power MOSFET Transistor Device Data
1

1 Page





20N03HL pdf, ピン配列
40
TJ = 25°C
30
VGS = 10 V
8V
TYPICAL ELECTRICAL CHARACTERISTICS
5 V 4.5 V
40
VDS 10 V
6V 4V
30
MTD20N03HDL
20
3.5 V
10
0
0
www.DataSheet4U.com
3V
2.5 V
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VDS, DRAIN–TO–SOURCE VOLTAGE (Volts)
Figure 1. On–Region Characteristics
20
10
100°C
25°C
0 TJ = – 55°C
1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0
VGS, GATE–TO–SOURCE VOLTAGE (Volts)
Figure 2. Transfer Characteristics
0.052
VGS = 5 V
0.044
TJ = 100°C
0.036
25°C
0.028
0.020
0
– 55°C
8 16 24 32
ID, DRAIN CURRENT (Amps)
40
Figure 3. On–Resistance versus Drain Current
and Temperature
0.036
TJ = 25°C
0.032
0.028
VGS = 5 V
0.024
10 V
0.020
0
8 16 24 32
ID, DRAIN CURRENT (Amps)
40
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1.8
VGS = 5 V
1.6 ID = 10 A
1.4
1.2
1.0
0.8
0.6
– 50 – 25
0 25 50 75 100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 5. On–Resistance Variation with
Temperature
150
1000
VGS = 0 V
100
TJ = 125°C
100°C
10
25°C
1
0 6 12 18 24 30
VDS, DRAIN–TO–SOURCE VOLTAGE (Volts)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3


3Pages


20N03HL 電子部品, 半導体
MTD20N03HDL
di/dt = 300 A/µs
Standard Cell Density
trr
High Cell Density
trr
ta tb
www.DataSheet4U.com
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance – Gen-
eral Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
100 µs
10
1 ms
10 ms
RDS(on) LIMIT
THERMAL LIMIT
dc
PACKAGE LIMIT
1
0.1 1.0 10 100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
200
ID = 20 A
160
120
80
40
0
25 50 75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
6 Motorola TMOS Power MOSFET Transistor Device Data

6 Page



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部品番号部品説明メーカ
20N03HL

MTD20N03HL

Motorola Semiconductors
Motorola Semiconductors


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