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PDF MC740-430E Data sheet ( Hoja de datos )
| Número de pieza | MC740-430E | |
| Descripción | 47-Gb/s 4:1 Multiplexer | |
| Fabricantes | ETC | |
| Logotipo |  |
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NEL
MD-01-4-43-75-482
May 8, 2002
Preliminary
MC740-430E
47-Gb/s 4:1 Multiplexer
The MC740-430E is an engineering sample of 47-Gb/s signal generator. It consists of a 4:1
multiplexer (MUX), D-type flipflop (D-FF), and clock distribution unit based on 0.1-µm InP-HEMT
devices. Four-parallel data inputs are multiplexed to 47-Gb/s data by using 47- and 11.75-GHz
clock signals. At the output stage, the D-FF regenerates the muliplexed data with the 47-GHz clock
signal and offers symmetrical eye openings. The MC740-430E has SCFL (Source Coupled FET
Logic) I/O and can be directly connected to a pulse pattern generator.
FEATURES
Operating range:
38 to 47 Gb/s (min.) (note)
Signal regeneration with full-rate clock signal
Large output amplitude:
SCFL I/O (VOHD = 0V, VOLD = -0.9V, typ.)
Single power supply voltage: DC -6 V
(note) 50-Gb/s operation is optional.
APPLICATIONS
Parallel-to-serial converters, Test equipments
FUNCTION DIAGRAM
20Gb/s 40Gb/s
(mon.) (mon.)
DATA 3, 2, 1, 0
4
CLK10
Latching stage
50 Ω
50 Ω
2 10-dB
ATT
75 Ω
4:1 MUX
D-FF
75 Ω
75 Ω
DATA
DATA
CLK10
2
Clock Distributor
65 Ω
φshifter
50 Ω CLK40
CLK40
50 Ω
Fig. 1. Function diagram.
-1-
1 page  
NEL
MC740-430E
RECOMMENDED OPERATING CONDITIONS
GENERAL
SYMBOL
PARAMETER
MIN. TYP. MAX. UNITS
VPWR (note1)
Power Supply Voltage
-6.0 V
Ta (note2)
Operating Temperature
20 - 30 ℃
(note1)
NEL recommends a DC power supply with an output current capacity of 10 A and an output voltage
ripple less than 10 mV rms.
(note2)
The MC740-430E should be protected from condensation.
DATA and CLOCK INPUT SIGNALS
SYMBOL
PARAMETER
DATA3 to 0
Data Input Interface
CLK40
CLK10
40-GHz Clock Input Interface
(with an internal DC blocking capacitor)
10-GHz Clock Input Interface
DATA and CLOCK OUTPUT SIGNALS
SYMBOL
PARAMETER
DATA,
/DATA
Data Output Interface
CLK40
40-GHz Clock Output Interface
(with an internal DC blocking capacitor)
CLK10
10-GHz Clock Output Interface
MONITOR OUTPUT SIGNALS
SYMBOL
PARAMETER
40Gb/s
40-Gb/s Monitor Output Interface
(with an internal 10-dB attenuator)
20 Gb/s
(odd, even)
CLK10
20-Gb/s Monitor Output Interface
10-GHz Clock Output Interface
Conditions
DC coupling
(see DC and AC characteristics)
AC coupling
(see AC characteristics)
AC or DC coupling
(see AC characteristics)
Conditions
DC coupling,
Terminate with 50 Ω to GND
AC coupling,
Terminate with 50 Ω
AC or DC coupling,
Terminate with 50 Ω
Conditions
DC coupling,
Terminate with 50 Ω to GND
DC coupling,
Terminate with 50 Ω to GND
AC or DC coupling,
Terminate with 50 Ω
-5-
5 Page 
NEL
MC740-430E
Step 1 CLK10 output
Insert a phase shifter between CLK10 output terminal and the PPG. Phase shift
range of the phase shifter should be 100 pspp.
Observe the 20 Gb/s monitor outputs by using the oscilloscope. If the CLK10 delay
is not optimum, the monitor outputs will be similar to Fig. 6(a). Adjust the CLK10
delay until the monitor output becomes clear (see Fig. 6(b)). When the 20G
monitor outputs become clear, the 40G monitor output automatically becomes clear.
20Gb/s odd
500 mV/div
20Gb/s even
500 mV/div
40Gb/s
150 mV/div
20Gb/s odd
500 mV/div
(a) with an unsuitable delay
20 psV/div
20Gb/s even
500 mV/div
40Gb/s
150 mV/div
Fig. 6.
20 psV/div
(b) after delay adjustment
20G and 40G monitor output waveforms.
Informally, similar adjustment could be done by shifting the delay of CLK10 input
(clock delay time from PPG). The output timing from the latching stage, or input
data timing for the 4:1 MUX, can be controlled by CLK10 input as shown in Fig. 7.
However, this method cannot be applicable for all situations because the clock phase
margin of the latching stage is smaller than 360 degree.
DATA 3, 2, 1, 0
4
CLK10 input
latched data
Latching
stage
4
4:1
MUX
internal clock
Fig. 7. Delay adjustment by CLK10 input.
- 11 -
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet MC740-430E.PDF ] | |
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