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STU2071 の電気的特性と機能

STU2071のメーカーはST Microelectronicsです、この部品の機能は「4B3T U INTERFACE CIRCUIT」です。


製品の詳細 ( Datasheet PDF )

部品番号 STU2071
部品説明 4B3T U INTERFACE CIRCUIT
メーカ ST Microelectronics
ロゴ ST Microelectronics ロゴ 




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STU2071 Datasheet, STU2071 PDF,ピン配置, 機能
STU2071
4B3T TWO-WIRE U INTERFACE CIRCUIT
FOR LT AND NT APPLICATION
120 kbaud LINE SYMBOL RATE (120 SYM-
BOLS PER FRAME)
SCRAMBLER AND DESCRAMBLER AC-
CORDING TO CCITT REC V.29
BARKER CODE (11 SYMBOLS) SYNCHRO-
NIZATION WORD
UNSCRAMBLED 1 KBIT/S HOUSEKEEPING
CHANNEL
ADAPTIVE ECHO CANCELLATION WITH
TRANSVERSAL FILTERING
ADAPTIVE DECISION FEEDBACK EQUALI-
ZATION
AUTOMATIC GAIN CONTROL
PDM AD CONVERTER
AUTOMATIC ACTIVATION AND DEACTIVA-
TION WITH POLARITY ADAPTION
AUTOMATIC CODE VIOLATION DETECTION
POWER FEED UNIT CONTROL
ADVANCED CL3 1.5µm CMOS PROCESS
28 PIN DUAL-IN-LINE PLASTIC PACKAGE
V* DIGITAL INTERFACE
4B3T U INTERFACE CIRCUIT
PRELIMINARY DATA
DIP28
ORDERING NUMBER: STU2071B1
PLCC28
ORDERING NUMBER: STU2071FN
SYSTEM OVERVIEW
STU2071 (UIC) provides two transparent 64 kbit/s
B channels, a transparent 16 kbit/s D channel, a
transparent 1 kbit/s service channel and a 1 kbit/s
maintenance channel for loop and error mes-
sages on subscriber lines.
UIC enables full duplex continuous data transmis-
sion via the standard twisted pair telephone ca-
ble. Adaptive Echo cancellation is used to restore
the received data. An equalizer, done with an
adaptive filter, restores the data which are dis-
torted by the transmission line.
The coefficient of the equalizer and echo cancel-
ler are conserved during a power down. An all
digital PLL performs both bit and frame synchroni-
zation.
The analog front end consists of receive path RX
and transmit path TX, providing a full duplex ana-
log interfacing to the twisted pair telephone cable.
Before data are converted to analog signals, they
pass through a digital filter (TX-filter) to reduce
the high frequency components. After D/A con-
version the signal is amplified and sent to the hy-
brid.
The received signal is converted back to digital
data and passed through the RX matching filter to
restore the line signal. The A/D convertor is a
second order sigma/delta modulator which oper-
ates with a clock of 15.36 MHz. After timing re-
covery, achieved by a digital PLL, the received
signal is equalized, in an adaptive digital filter, to
correct for the frequency and group delay distor-
tion of the line.
Power supply status can be read via PFOFF. The
UIC can disable its power supply (DISS), and two
relay drivers outputs are provided (accessible via
B2*) to control the power feed unit (RD1,RD2).
September 1994
1/18
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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STU2071 pdf, ピン配列
STU2071
PIN DESCRIPTION
Pin Name
1 DVSS(input)
2 PFOFF(input)
3 LT(input)
4 TEST(input)
5 DISS(output)
6 RESETN(input)
7 DIN(input)
8 TSP(input)
9
10
11
12
13
14
15, 16, 17
18
19
20
21
22
23
24,25
26, 27
28
BURST(input)
FR(in/out)
DOUT(output)
CL(in/out)
RD1(output)
RD2(output)
S2,S1,S0
DVDD(input)
AVSS(input)
LOUT1(output)
AVDD(input)
AGND(input)
LOUT2(output)
LIN1,LIN2(input)
XTAL1,XTAL2(inputs)
CLS(output)
Function
Digital Ground.
Power feed off. PFOFF=HIGH is coded by the A-bit indication HI
accessible on DOUT. Active in LT mode only.
LT/NT mode selection.
Test Mode.
A bit channel driven pin. Active in LT mode only.
Hardware Reset.
Digital interface input.
Transmit single pulse. 1 KHz single pulse alternating positive and
negative polarity is transmitted.
Burst mode selection. Active in LT mode only.
8KHz Digital interface frame clock; input in LT and output in NT mode.
Digital interface output.
Digital interface bit clock; input in LT and output in NT mode.
Power feeder relay driver.
Power feeder relay driver.
Time slot pin strap (. Active in LT mode only.
5V +/-5% positive digital power supply.
Analog Ground.
Output to the line.
5V +/-5% positive analog power supply.
Analog Ground.
Output to the line.
Inputs from the line (UK0).
System clock input;nominal frequency is 15.36MHz.
Clock output synchronous to the line receive clock at 7.68MHz.
APPLICATION AND MODES
The UIC can be used in LT, LT-burst and in NT
mode.
Hereafter a list of the pin bias to set up the de-
sired mode is given.
In LT mode:
Pins
LT
BURST
S0
S1
S2
Value
1
0
0
0
0
In LT burst:
Pins
LT
BURST
S0
S1
S2
Value
1
1
time slot
time slot
time slot
In NT:
Pins
Value
LT
BURST
S0
S1
S2
0
0
0
0
1
Test pins should always be tied to GND
3/18


3Pages


STU2071 電子部品, 半導体
STU2071
LT burst mode
Figure 4: LT Burst Mode Schematic Application Diagram.
DIN:
DOUT:
CL:
FR:
XTAL2:
CLS:
6/18
Data input, datarate = 2048 kbit/s, continuous
Data output, datarate = 2048 kbit/s, continuous
Data clock input, f = 4096 KHz
Frame clock input, f = 8 KHz (1:1)
System clock input, f = 15.36 MHz (Tx clock synchronous to system clock)
Clock output, 7.68 MHz

6 Page



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部品番号部品説明メーカ
STU2071

4B3T U INTERFACE CIRCUIT

ST Microelectronics
ST Microelectronics


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